T48C893 datasheet(58/82 Pages) ATMEL

58 / 82 page

T48C893

Rev. A4, 22-Jan-02

58 (82)

configurations, the SSI, in I2C mode is intended for use

purely as a master controller on a single master bus

system. So all reference to multiple bus control and bus

contention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing

handshaking

acknowledge-bit.

Normally

the

communication channel is opened with a so-called start

condition, which initializes all devices connected to the

bus. This is then followed by a data telegram, transmitted

by the master controller device. This telegram usually

contains an 8-bit address code to activate a single slave

device connected onto the I2C bus. Each slave receives

this address and compares it with it’s own unique address.

The addressed slave device, if ready to receive data will

respond by pulling the SD line low during the 9th clock

pulse. This represents a so-called I2C acknowledge. The

controller on detecting this affirmative acknowledge then

opens a connection to the required slave. Data can then be

passed back and forth by the master controller, each 8-bit

telegram being acknowledged by the respective recipient.

The communication is finally closed by the master device

and the slave device put back into standby by applying a

stop condition onto the bus.

(2)

(1)

(4)

(3)

(1)

Start

condition

Data

valid

Data

change

Data

valid

Stop

condition

13832

Figure 64. I2C bus protocol 1

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while

the clock (SC) is HIGH defines a START

condition.

Stop data transfer (3)

A LOW to HIGH transition of the SD line while

the clock (SC) is HIGH defines a STOP condition.

Data valid (4)

The state of the data line represents valid data

when, after START condition, the data line is

stable for the duration of the HIGH period of the

clock signal.

Acknowledge

All address and data words are serially transmitted

to and from device in eight–bit words. The

receiving device returns a zero on the data line

during the ninth clock cycle to acknowledge word

receipt.

13833

Start

1st Bit

8th Bit

ACK

Stop

Figure 65. I2C bus protocol 2

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