T48C893 datasheet(59/82 Pages) ATMEL

59 / 82 page

T48C893

Rev. A4, 22-Jan-02

59 (82)

SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI

buffer register status (i.e., transmit buffer empty or

receive buffer full) end of SSI data telegram or on the

falling edge of the SC/SD pins on Port 4 (see P4CR). SSI

interrupt selection is performed by the Interrupt FunctioN

control bit (IFN). The SSI interrupt is usually used to

synchronize the software control of the SSI and inform

the controller of the present SSI status. The Port 4

interrupts can be used together with the SSI or, if the SSI

itself is not required, as additional external interrupt

sources. In either case this interrupt is capable of waking

the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the

SSI interrupt mask (SIM) and the Interrupt Function

(IFN) while the Port 4 interrupts are enabled by setting

appropriate control bits in P4CR register.

Modulation and Demodulation

If the shift register is used together with Timer 2 or

Timer 3 for modulation or demodulation purposes, the

8-bit synchronous mode must be used. In this case, the

unused Port 4 pins can be used as conventional

bidirectional ports.

The modulation and demodulation stages, if enabled,

operate as soon as the SSI is activated (SIR=0) and cease

when deactivated (SIR=1).

Due to the byte-orientated data control, the SSI when

running normally generates serial bit streams which are

submultiples of 8 bits. An SSI output masking (OMSK)

function permits, however, the generation of bit streams

of any length. The OMSK signal is derived indirectly

from the 4-bit prescaler of the Timer 2 and masks out a

programmable number of unrequired trailing data bits

during the shifting out of the final data word in the bit

stream. The number of non-masked data bits is defined by

the value pre-programmed in the prescaler compare

bit (MSM) must be set to ’0’ before programming the

final data word into the SSI transmit buffer. This in turn,

enables shift clocks to the prescaler when this final word

is shifted out. On reaching the compare value, the

prescaler triggers the OMSK signal and all following data

bits are blanked.

Internal 2-Wire Multi-Chip Link

Two additional on-chip pads (MCL_SC and MCL_SD)

for the SC and the SD line can be used as chip-to-chip link

for multi-chip applications. These pads can be activated

by setting the MCL-bit in the SISC-register. They are also

used as interface to the internal data EEPROM

SCL

SDA

MCL_SC

MCL_SD

U505M

VDD

BP40/SC

BP10

BP43/SD

BP13

Multi chip link

VSS

T48C893

Figure 66. Multi-chip link

13834

8-bit shift register

MSB

LSB

Shift_CL

Control

Timer 2

Output

SSI-control

Compare 2/1

4-bit counter 2/1

CL2/1

SCL

CM1

OMSK

TOG2

POUT

T1OUT

SYSCL

Figure 67. SSI output masking function

T48C893 Datasheet(PDF) 59 Page - ATMEL Corporation

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