T48C893 datasheet(17/82 Pages) ATMEL

17 / 82 page

T48C893

Rev. A4, 22-Jan-02

17 (82)

3.5

Clock Generation

3.5.1

Clock Module

The T48C893 contains a clock module with 4 different

internal oscillator types: two RC-oscillators, one 4-MHz

crystal oscillator and one 32-kHz crystal oscillator. The

pins OSC1 and OSC2 are the interface to connect a crystal

either to the 4-MHz, or to the 32-kHz crystal oscillator.

OSC1 can be used as input for external clocks or to

connect

external

trimming

resistor

for

the

RC-oscillator 2. All necessary circuitry except the crystal

and the trimming resistor is integrated on-chip. One of

these oscillator types or an external input clock can be

selected to generate the system clock (SYSCL).

In applications that do not require exact timing, it is

possible to use the fully integrated RC-oscillator 1

without any external components. The RC-oscillator 1

center frequency tolerance is better than

± 50%. The

RC-oscillator 2 is a trimmable oscillator whereby the

oscillator frequency can be trimmed with an external

resistor attached between OSC1 and VDD. In this

configuration, the RC-oscillator 2 frequency can be

maintained stable to within a tolerance of

± 15% over the

full operating temperature and voltage range.

The clock module is programmable via software with the

clock management register (CM) and the system

configuration register (SC). The required oscillator

configuration can be selected with the OS1-bit and the

OS0-bit in the SC-register. A programmable 4-bit divider

stage allows the adjustment of the system clock speed. A

special feature of the clock management is that an

external oscillator may be used and switched on and off

via a port pin for the power-down mode. Before the

external clock is switched off, the internal RC-oscillator

1 must be selected with the CCS-bit and then the SLEEP

mode may be activated. In this state an interrupt can wake

up the controller with the RC-oscillator, and the external

oscillator can be activated and selected by software. A

synchronization stage avoids too short clock periods if the

clock source or the clock speed is changed. If an external

input clock is selected, a supervisor circuit monitors the

external input and generates a hardware reset if the

external clock source fails or drops below 500 kHz for

more than 1 msec.

Ext. clock

ExIn

ExOut

Stop

RC oscillator2

RCOut2

Stop

Trim

4–MHz oscillator

4Out

Stop

Oscin

Oscout

Oscin

Oscout

32–kHz oscillator

32Out

Oscin

Oscout

oscillator 1

RCOut1

Control

Stop

IN1

IN2

Cin

Divider

Sleep

WDL

Osc–Stop

NSTOP

CCS

CSS1

CSS0

CM:

BOT

– – –

OS1

OS0

SUBCL

SYSCL

SC:

OSC1

OSC2

configurable

Cin/16

32 kHz

Figure 14. Clock module

Table 4 Clock modes

Mode

Clock Source for SYSCL

Clock Source for SUBCL

OS1

OS0

CCS = 1

CCS = 0

RC-oscillator 1 (intern)

External input clock

Cin / 16

RC-oscillator 1 (intern)

RC-oscillator 2 with

external trimming resistor

Cin / 16

RC-oscillator 1 (intern)

4-MHz oscillator

Cin / 16

RC-oscillator 1 (intern)

32-kHz oscillator

32 kHz

T48C893 Datasheet(PDF) 17 Page - ATMEL Corporation

T48C893 Datasheet(HTML) 17 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL