TVP3020 datasheet(37/98 Pages) TI

37 / 98 page

2–23

2.5

On-Chip Cursor

The Viewpoint palette has an on-chip two-color 64 x 64 pixel user-definable cursor. The cursor operation

defaults to the XGA standard, but X-Windows compatibility is also available (see Section 2.5.2). In addition

to the 64

× 64 sprite cursor, TVP3020 also supports a two-color crosshair cursor. The cursors only operate

in noninterlaced applications.

The pattern for the 64

× 64 cursor is provided by the cursor RAM, which may be accessed by the MPU at

any time. Cursor positioning is performed via the cursor-position (x,y) registers and the sprite-origin (x,y)

registers (see register bit definitions in Sections 2.16.3 and 2.16.4). Positions x and y are defined in the

palette increasing from left to right and from top to bottom, respectively, as seen on the display screen. The

cursor position (x,y) is relative to the first pixel displayed. In other words, the very first pixel displayed is

located at position (0,0), and the last pixel displayed for a 1024

× 768 system is located at position (1023,

767).

On-chip cursor control is performed by the cursor-control register in the indirect register map (06 hex). Bits

0 and 1 control the width of the crosshair (1, 3, 5, or 7 pixels). Bit 2 enables/disables the crosshair cursor,

and bit 3 controls the crosshair-cursor color. Bit 4 specifies either XGA or X-window mode for the sprite

cursor. Bit 5 controls the color at the intersection of the sprite and crosshair cursors, and bit 6

enables/disables the sprite cursor. See the cursor-control register bit definitions in Section 2.16.2 for more

details.

2.5.1

Cursor RAM

The 64

× 64 × 2 cursor RAM is used to define the pixel pattern within the 64 × 64 pixel cursor window. It is

not initialized and may be written to or read by the MPU at any time. The cursor-RAM address zero is at the

top left corner of the RAM as shown in Figure 2–6.

The cursor RAM is written to by loading a number into the cursor RAM. Address registers 09 and 08 (hex)

of the index register indicate the location of the first group of four cursor pixels to be updated (two bits per

pixel implies four pixels per byte). Then the first four pixels are written to the cursor-RAM data register 0A

(hex) of the index register. This stores the cursor pixel data in the cursor RAM and automatically increments

the cursor-RAM address register. A second write to the cursor-RAM data register then loads the next four

cursor pixels, and so on. See the register bit definitions in Sections 2.16.8 and 2.16.9.

To read from the cursor RAM, the address of the first cursor-RAM location to be read is loaded into the

cursor-RAM address registers. Then a read is performed on the cursor-RAM data register [0A (hex) of the

Index register]. Similar to the cursor-RAM write operation, when the read is completed the cursor-RAM

address register is automatically incremented and further reads read successive cursor RAM locations.

The cursor RAM is written and read using the same hardware registers, so any task updating either of these

on an interrupt thread must save and restore the cursor-RAM address LSB [Index 08 (hex)] and cursor-RAM

address MSB [Index 09 (hex)] registers.

NOTES: When the cursor-RAM address is to be written, always write both the

cursor-RAM address LS and MS registers with the cursor-RAM address LSB

It is recommended that the cursor RAM not be accessed while the sprite cursor is

enabled; otherwise, there is a possibility that the cursor RAM could be corrupted.

Therefore, the sprite cursor should be temporarily disabled [cursor-control register

(CCR) bit 6 = 0] when writing to or reading from the cursor RAM.

The cursor-generation logic requires the use of active low sync inputs.

Vertical retrace is determined by detecting multiple syncs in blank.

The video front-porch time must be at least one RCLK period. The video

back-porch time must be at least 80 pixel clock periods.

TVP3020 Datasheet(PDF) 37 Page - Texas Instruments

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