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TVP3020 Datasheet(PDF) 24 Page - Texas Instruments

Part # TVP3020
Description  Video Interface Palette
PDF  98 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TVP3020 Datasheet(HTML) 24 Page - Texas Instruments

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2–10
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
BLNK
(internal signal
before DOTCLK
pipeline delay)
PIXEL DATA
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
Latch Last Group
of Pixel Data
SFLAG Input
Last
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
1st Group of
Pixel Data
SCLK Between Split Shift Register and Regular Shift Register Transfer
Figure 2–3. SCLK/VCLK Control Timing
(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
BLNK
(internal signal
before DOTCLK
pipeline delay)
PIXEL DATA
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch first Group of Pixel Data
1st
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
Last Group of Pixel Data
7th
Group
Figure 2–4. SCLK/VCLK Control Timing
(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)



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