TVP3020 datasheet(19/98 Pages) TI

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2–5

The ECL input can be used as a differential or single-ended input. If CLK2 is used as a single-ended ECL

input, CLK2 needs to be externally terminated to set the input common-mode signal level. This can be done

with a simple resistor divided, as is the case with fully differential ECL. Care needs to be taken when

choosing the resistor values to ensure that the dc level on CLK2 is in the middle of the CLK2 ECL-input signal

range.

2.3.1

RCLK, SCLK, VCLK

The Viewpoint VIP provides user-programmable reference clock (RCLK), shift clock (SCLK), and video

(VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously running reference

clock and is not disabled during blank. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or 64 of the

dot clock (see Table 2–5). It is provided as a clock reference and is typically connected back to the LCLK

input to latch pixel-port data. Since pixel-port data is latched on the rising edge of LCLK, the RCLK frequency

must be set as a function of the desired multiplexing ratio (that depends on the pixel bus width and number

of bit planes). See Section 2.4 and Table 2–6.

SCLK is the same as RCLK but disabled during the blank active period. SCLK is designed to be used as

the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and

held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing

is discussed in Section 2.3.2 and illustrated in Figures 2–2 through 2–5.

VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed

control logic to generate the graphics system control signals (SYSBL, SYSHS, and SYSVS). VCLK can be

selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at logic 1 (see Table 2–5).

The default setup is VCLK held at logic 1 since it is not used in VGA pass-through mode. Since these control

signals are sampled by VCLK, VCLK must be enabled for these to function properly (see Figures 2–2

through 2–5).

Even though RCLK /SCLK and VCLK can be selected independently, there is still a relationship between

the two as discussed below. Many system considerations have been carefully covered in their design,

leaving maximum freedom to the user.

Internally, RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising

edge of the DOTCLK. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as

shown in Figure 2–1.

The internal clock counter is initialized any time the output-clock-selection register is written with 3F (hex).

This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known

phase relationship for the various system clocks. It is left up to the user to provide some means of disabling

the dot clock input to the part while this reset is occurring if multiple parts are to be synchronized.

The reset default divide ratio for RCLK is 64:1 with SCLK held at logic 0 and VCLK held at logic 1.

When choosing certain video timing parameters, exercise caution if the selected RCLK frequency is less

than the selected VCLK frequency. Refer to Appendix B for a more detailed discussion.

DOTCLK

VCLK

(DOTCLK/4 as an example)

RCLK = SCLK

(DOTCLK/2 as an example)

Figure 2–1. DOTCLK / VCLK / RCLK / SCLK Relationship

The input-clock-selection register is used to select the desired input clock source. Table 2–4 details how to

program the various options.

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