TVP3020 datasheet(17/98 Pages) TI

17 / 98 page

2–3

Table 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

R/W

DEFAULT

(HEX)

BY INDEX REGISTER

R/W

Color-Key Blue Low

R/W

Color-Key Blue High

R/W

Color-Key Control Register

Reserved-Undefined

R/W

Sense Test Register

Test Data Register

CRC LSB

CRC MSB

CRC Control Register

ID Register

Reset Register

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on

the register map.

2.2

Color Palette

The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.

This register is automatically incremented following a RAM transfer, allowing the entire palette to be

read/written with only one access of the address register. When the address register increments beyond

the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM

are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not

cause any noticeable disturbance on the display.

The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is eight

bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6 = 0).

If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.

However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and

Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s

after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC

calculation both take data after the output multiplexer, enabling total system verification. The color palette

access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.

2.2.1

Writing to Color-Palette RAM

To load the color palette, the MPU must first write to the address register (write mode) with the address where

the modification is to start. This is then followed by three successive writes to the palette holding register

with 8 bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are

concatenated into a 24-bit word that is then written to the RAM location specified by the address register.

The address register then increments to the next location, which the MPU may modify by simply writing

another sequence of red, green, and blue data. A block of color values in consecutive locations may be

written to by writing the start address and performing continuous red, green, and blue write cycles until the

entire block has been written.

2.2.2

Reading From Color-Palette RAM

Reading from the palette is performed by writing to the address register (read mode) with the location to be

read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment

of the address register. Three successive MPU reads from the holding register produce red, green, and blue

color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the blue read cycle,

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