TVP3020 datasheet(32/98 Pages) TI

32 / 98 page

2–18

Table 2–7. Pseudo-Color Mode Pixel-Latching Sequence (see Notes 13 and 14)

VGA7–VGA0

P1, P0

P1 – P0

P3, P2

P3 – P2

P5 – P4

•

P7 – P6

•

P15

P31

P63

s10

s11

s12

s13

s14

s15

P1 – P0

P3 – P0

P3 – P2

P7 – P4

P5 – P4

P11 – P8

•

P15 – P12

•

P15 – P14

P31 – P30

P63 – P62

P31 – P28

P63 – P60

s16

s17

s18

s19

P7 – P0

P15 – P8

P23 – P16

P31 – P24

•

P63 – P56

NOTES: 13. The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups of data

are latched, the LCLK rising edge latches all the groups and the pixel clock shifts them out starting with the

low-numbered group. For example, in pseudo-color submode 3 with a 16-bit pixel bus width, the rising edge

of LCLK latches all the data groups shown above (s13) and the pixel clock shifts them out in the order

P(3 – 0), P(7 – 4), P(11 – 8), and P(15 – 12). Note that each line in each subtable above represents one pixel.

14. When in the big-endian format (GCR3 =1), the pixel bus is externally swapped by the user (i.e., D63

connected to P0, D0 connected to P63). Since data is always shifted out from low-numbered groups to

high-numbered groups, the external swapping of the pixel bus causes the groups to be shifted out in the

correct order. However, for modes with more than one bit per pixel, the bits in each data group are reversed

(LSB to MSB). This is internally corrected by the Viewpoint input multiplexer. The difference between big-

and little-endian data formats and how they affect the pixel bus operation is discussed in more detail in

Appendix C.

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