TVP3020 datasheet(30/98 Pages) TI

30 / 98 page

2–16

Table 2–6. Multiplex Mode and Bus-Width Selection (Continued)

MODE

SUB-

MODE

MULTIPLEX-

CONTROL

(HEX)

MULTIPLEX-

CONTROL

(HEX)

DATA

BITS

PER

PIXEL

(see

Note 8)

PIXEL

BUS

WIDTH

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLAY

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

24-bit

(5 – 6 – 5)

XGA

Direct

(5 – 5 – 5)

TARGA

d10

d11

16-bit

d12

(6 – 6 – 4)

d13

d14

12-bit

d15

(4 – 4 – 4)

d16

NOTES:

9. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

often referred to as the number of bit planes.

10. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each

LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists

of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.

Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK

divide ratio is not automatically set by mode selection but must be programmed in the output clock selection

11. This column is a reference to Tables 2–8 through 2–11, where the actual manipulation of pixel information

and pixel latching sequences are illustrated for each of the multiplexing modes.

12. It is recommended that all unused input terminals be connected to ground to conserve power.

13. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window

or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as

programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with

direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control

programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values

should be programmed as indicated in Table 2–6 for VGA mode.

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