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TVP3020 Datasheet(PDF) 67 Page - Texas Instruments

Part # TVP3020
Description  Video Interface Palette
PDF  98 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TVP3020 Datasheet(HTML) 67 Page - Texas Instruments

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3–5
3.6 Switching Characteristics
PARAMETER
TVP3020-135
UNIT
PARAMETER
MIN
TYP
MAX
UNIT
SCLK frequency (CLOAD ≤ 15 pF) (see Note 10)
85
MHz
SCLK frequency (CLOAD ≤ 60 pF) (see Note 10)
85
MHz
RCLK/VCLK frequency (see Note 10)
85
MHz
ten1
Enable time, RD low to D(0 – 7) valid
40
ns
tdis1
Disable time, RD high to D(0 – 7) disabled
17
ns
tv1
Valid time, D(0 – 7) valid after RD high
5
ns
tPLH1 Propagation delay, SFLAG↑ to SCLK high (see Note 10 and 11)
0
20
ns
td1
Delay time, RD low to D(0 – 7) starting to turn on
5
ns
td2
Delay time, selected input clock high/low to DOTCLK (internal signal)
high/low
7
ns
td3
Delay time, SCLK high/low to RCLK high/low (see Note 12)
1
2
5
ns
td4
Delay time, VCLK high/low to RCLK high/low (see Note 12)
1
3
6
ns
td5
Delay time, RCLK high/low from DOTCLK high/low (internal signal)
7
ns
td6
Delay time, LCLK from RCLK
tRCLK-7
ns
td7
Delay time, DOTCLK high to IOR/IOG/IOB active (analog output
delay time) (see Note 13)
4
ns
td8
Analog output settling time (see Note 14)
6
ns
td9
Delay time, DOTCLK high to HSYNCOUT and VSYNCOUT valid
9
ns
tr
Analog output rise time (see Note 15)
2
ns
Analog output skew
0
2
ns
NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns (typical 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF,
with worst case transition times between 10% and 90% levels less than 4 ns (typical 3 ns).
11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.15
for details.
12. The SCLK and VCLK delay time to RCLK depends on the load that the signals drive. This parameter is
measured with an RCLK to VCLK ratio of 1:1, and VCLK = RCLK load of 15 pF and SCLK load of 60 pF.
13. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
14. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
15. Measured between 10% and 90% of the full-scale transition.



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