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AD9542 Datasheet(PDF) 33 Page - Analog Devices

Part # AD9542
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542 Datasheet(HTML) 33 Page - Analog Devices

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Data Sheet
AD9542
Rev. 0 | Page 33 of 61
SMALL CELL BASE STATION
In this application (shown in Figure 42), the AD9542 provides
all of the synchronization to the baseband unit of a small cell
base station. The built in JESD204B support enables a particu-
larly compact and efficient design.
The AD9542 can lock to any of the following: GPS, SyncE,
and/or IEEE1588 (requires a separate IEEE1588 servo and
software stack) or loop timed (if using SONET/SDH backhaul).
The PLL0 of the AD9542 provides one device clock and up to
four device system reference clocks that can be used to clock
wireless transceivers, such as the AD9371.
The PLL1 of the AD9542 clocks the backhaul interface and,
optionally, the CPU interface.
The EEPROM support of the AD9542 allows the AD9542 to
load its configuration automatically at power-up.
BASEBAND
PROCESSOR
UP TO TWO
RADIO CARDS
(INCLUDING AD9371
TRANSCEIVER)
NETWORK
CONNECTION
INPUT
LOOP-TIMED/SyncE
FROM NETWORK
30.72MHz/
61.44MHz/
122.88MHz
WITH JESD204B
SUPPORT
30.72MHz/61.44MHz/
122.88MHz/245.76MHz/
307.2MHz
DIFF/SE OUTPUTS
<300fs OF JITTER
10 MHz/25MHz/
125 MHz/156.25MHz/
312.5MHz DIFF/SE
OUTPUTS
<300fs OF JITTER
EXTERNAL
NETWORK
CONNECTION
ETHERNET
SyncE
PON
SONET/SDH
SYSREF TO
RADIO 1
SYSREF TO
RADIO 2
SYSREF TO
BASEBAND
CLOCK
MULTIPLIER
CLOCK DRIFT
COMPENSATION
CONTROL
LOGIC
ANALOG
PLL1
DIGITAL
PLL1
/Q1B + PPS
/Q1A + PPS
/Q0C + PPS
/Q0B SYSREF
/Q0B SYSREF
/Q0A SYSREF
/Q0A SYSREF
SERIAL PORT
(SPI OR I2C)
CSB, SCLK/SCL,
SDIO/SDA, SDO
STATUS AND
CONTROL PINS
EEPROM
CONTROLLER
Mx PINS
DIGITAL
PLL0
ANALOG
PLL0
REFA/AA
REFB/BB
AD9542
NEXT GENERATION SYNCHRONIZER
1:4
FANOUT
EXTERNAL
EEPROM
(OPTIONAL)
Figure 42. Small Cell Application



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