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AD9542 Datasheet(PDF) 41 Page - Analog Devices |
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AD9542 Datasheet(HTML) 41 Page - Analog Devices |
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41 / 61 page  Data Sheet AD9542 Rev. 0 | Page 41 of 61 Bits[D6:D0] (Hex) Control Function Destination Proxy Status Function Source Proxy (or Description) 0x3C Unassigned Not applicable PLL0 distribution synchronized Register 0x3013, Bit D4 0x3D Unassigned Not applicable Unassigned Not applicable 0x3E Unassigned Not applicable DPLL0 phase step detected Register 0x3010, Bit D0 0x3F Unassigned Not applicable DPLL0 fast acquisition active Register 0x3102, Bit D4 0x40 PLL0 power-down Register 0x2100, Bit D0 DPLL0 fast acquisition complete Register 0x3102, Bit D5 0x41 DPLL0 user freerun Register 0x2105, Bit D0 DPLL0 feedback divider resync Register 0x3012, Bit D4 0x42 DPLL0 user holdover Register 0x2105, Bit D1 PLL0 distribution phase slew enable Indicates when any one of the PLL0 distribution phase slew limiters is actively limiting 0x43 DPLL0 clear tuning word history Register 0x2107, Bit D1 PLL0 distribution configuration error Indicates when any one of the PLL0 distribution channel dividers encountered a phase offset error 0x44 Synchronize PLL0 distribution dividers Register 0x2101, Bit D3 Unassigned Not applicable 0x45 DPLL0 translation profile select, Bit 0 Register 0x2105, Bit D4 Unassigned Not applicable 0x46 DPLL0 translation profile select, Bit 1 Register 0x2105, Bit D5 Unassigned Not applicable 0x47 DPLL0 translation profile select, Bit 2 Register 0x2105, Bit D6 Unassigned Not applicable 0x48 Unassigned Not applicable Unassigned Not applicable 0x49 Unassigned Not applicable Unassigned Not applicable 0x4A Unassigned Not applicable Unassigned Not applicable 0x4B Unassigned Not applicable Unassigned Not applicable 0x4C Unassigned Not applicable Unassigned Not applicable 0x4D Unassigned Not applicable Unassigned Not applicable 0x4E Unassigned Not applicable Unassigned Not applicable 0x4F Unassigned Not applicable Unassigned Not applicable 0x50 Mute OUT0A Register 0x2102, Bit D2 DPLL1 phase locked Register 0x3200, Bit D1 0x51 Mute OUT0AA Register 0x2102, Bit D3 DPLL1 frequency locked Register 0x3200, Bit D2 0x52 Reset OUT0A/ OUT0AA driver Register 0x2102, Bit D5 APLL1 locked Register 0x3200, Bit D3 0x53 Mute OUT0B Register 0x2103, Bit D2 APLL1 calibration in progress Register 0x3200, Bit D4 0x54 Mute OUT0BB Register 0x2103, Bit D3 DPLL1 active Register 0x300A, Bit D5 || Bit D4 || Bit D3 || Bit D2 || Bit D1 || Bit D0 0x55 Reset OUT0B/ OUT0BB driver Register 0x2103, Bit D5 DPLL1 freerun Register 0x3201, Bit D0 0x56 Mute OUT0C Register 0x2104, Bit D2 DPLL1 holdover Register 0x3201, Bit D1 0x57 Mute OUT0CC Register 0x2104, Bit D3 DPLL1 switching Register 0x3201, Bit D2 0x58 Reset OUT0C/ OUT0CC driver Register 0x2104, Bit D5 DPLL1 tuning word history status Register 0x3202, Bit D0 0x59 Mute OUT0xP/ OUT0xN Register 0x2101, Bit D1 DPLL1 tuning word history updated Register 0x3015, Bit D2 0x5A Reset OUT0xP/ OUT0xN drivers Register 0x2101, Bit D2 DPLL1 frequency clamped Register 0x3202, Bit D1 0x5B Channel 0 N-shot request Register 0x2101, Bit D0 DPLL1 phase slew limited Register 0x3202, Bit D2 0x5C Unassigned Not applicable PLL1 distribution synchronized Register 0x3018, Bit D4 0x5D Unassigned Not applicable Unassigned Not applicable |
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