AD9542 datasheet(57/61 Pages) AD

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Data Sheet

AD9542

Rev. 0 | Page 57 of 61

DATA BIT N – 1

DATA BIT N

CSB

SCLK

SDIO

SDO

tDV

Figure 56. Timing Diagram for Serial Control Port Register Read—MSB First

CSB

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1 A2 A3

A5 A6

A9 A10 A11 A12

R/W

A14

A13

D5 D6

D1 D2

D4 D5

Figure 57. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 58. Serial Control Port Timing—Write

Table 36. Serial Control Port Timing

Parameter

Description

Setup time between data and the rising edge of SCLK

Hold time between data and the rising edge of SCLK

CLK

Period of the clock

Setup time between the CSB falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CSB rising edge (end of the communication cycle)

HIGH

Minimum period that SCLK is in a logic high state

LOW

Minimum period that SCLK is in a logic low state

SCLK to valid SDIO (see Figure 56)

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