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AD9542 Datasheet(PDF) 42 Page - Analog Devices

Part # AD9542
Description  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9542 Datasheet(HTML) 42 Page - Analog Devices

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AD9542
Data Sheet
Rev. 0 | Page 42 of 61
Bits[D6:D0]
(Hex)
Control Function
Destination Proxy
Status Function
Source Proxy (or Description)
0x5E
Unassigned
Not applicable
DPLL1 phase step
detected
Register 0x3015, Bit D0
0x5F
Unassigned
Not applicable
DPLL1 fast acquisition
active
Register 0x3202, Bit D4
0x60
PLL1 power-down
Register 0x2200, Bit D0
DPLL1 fast acquisition
complete
Register 0x3202, Bit D5
0x61
DPLL1 force freerun
Register 0x2205, Bit D0
DPLL1 feedback divider
resync
Register 0x3017, Bit D4
0x62
DPLL1 force holdover
Register 0x2205, Bit D1
PLL1 distribution phase
slew enable OR’ed
Indicates when any one of the PLL1
distribution phase slew limiters is actively
limiting
0x63
DPLL1 clear tuning
word history
Register 0x2207, Bit D1
PLL1 distribution phase
control error OR’ed
Indicates when any one of the PLL1
distribution channel dividers
encountered a phase offset error
0x64
Synchronize PLL1
distribution dividers
Register 0x2201, Bit D3
Unassigned
Not applicable
0x65
DPLL1 translation
profile select, Bit 0
Register 0x2205, Bit D4
Unassigned
Not applicable
0x66
DPLL1 translation
profile select, Bit 1
Register 0x2205, Bit D5
Unassigned
Not applicable
0x67
DPLL1 translation
profile select, Bit 2
Register 0x2205, Bit D6
Unassigned
Not applicable
0x68
Unassigned
Not applicable
Unassigned
Not applicable
0x69
Unassigned
Not applicable
Unassigned
Not applicable
0x6A
Unassigned
Not applicable
Unassigned
Not applicable
0x6B
Unassigned
Not applicable
Unassigned
Not applicable
0x6C
Unassigned
Not applicable
Unassigned
Not applicable
0x6D
Unassigned
Not applicable
Unassigned
Not applicable
0x6E
Unassigned
Not applicable
Unassigned
Not applicable
0x6F
Unassigned
Not applicable
Unassigned
Not applicable
0x70
Mute OUT1A
Register 0x2202, Bit D2
Not applicable
Not applicable
0x71
Mute OUT1AA
Register 0x2202, Bit D3
Not applicable
Not applicable
0x72
Reset OUT1A/OUT1AA
driver
Register 0x2202, Bit D5
Not applicable
0x73
Mute OUT1B
Register 0x2203, Bit D2
Not applicable
0x74
Mute OUT1BB
Register 0x2203, Bit D3
Not applicable
0x75
Reset OUT1B/OUT1BB
driver
Register 0x2203, Bit D5
Not applicable
0x76
Mute OUT1xP/OUT1xN
drivers
Register 0x2201, Bit D1
Unassigned
Not applicable
0x77
Reset OUT1xP/OUT1xN
drivers
Register 0x2201, Bit D2
Unassigned
Not applicable
0x78
Channel 1 N-shot
request
Register 0x2201, Bit D0
Timestamp 0 event
detected
Register 0x300E, Bit D2
0x79
Unassigned
Not applicable
Timestamp 1 event
detected
Register 0x300E, Bit D3
0x7A
Unassigned
Not applicable
Skew measurement
detected
Register 0x300E, Bit D4
0x7B
Unassigned
Not applicable
Unassigned
Not applicable
0x7C
Unassigned
Not applicable
Unassigned
Not applicable
0x7D
Unassigned
Not applicable
Unassigned
Not applicable
0x7E
Unassigned
Not applicable
Unassigned
Not applicable
0x7F
Unassigned
Not applicable
Unassigned
Not applicable



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