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LPC47M192 Datasheet(PDF) 159 Page - SMSC Corporation |
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LPC47M192 Datasheet(HTML) 159 Page - SMSC Corporation |
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159 / 228 page ![]() SMSC DS – LPC47M192 Page 159 Rev. 03/30/05 DATASHEET NAME REG OFFSET (hex) DESCRIPTION GP43 Default = 0x01 on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and PCI Reset 3E (R/W) General Purpose I/0 bit 4.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Either Edge Triggered Interrupt Input 3 (Note 1) 10=Reserved 01=Device Disable Register Control. The GP43 pin is an input, with non-inverted polarity. When bits[3:2]=01, they cannot be changed by writing to these bits; they are cleared by VCC POR, PCI Reset and VTR POR. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a VCC POR, PCI Reset or VTR POR. The Device Disable register is controlled by the value of the GP43 pin as follows: If the GP43 pin is high, the Device Disable Register is Read-Only. If the GP43 pin is low, the Device Disable Register is Read/Write. 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull GP50 Default = 0x01 on VTR POR 3F (R/W) General Purpose I/0 bit 5.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nRI2 (User Note 1) 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull GP51 Default = 0x01 on VTR POR 40 (R/W) General Purpose I/0 bit 5.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nDCD2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull |
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