LPC47M192 datasheet(219/228 Pages) SMSC

219 / 228 page

SMSC DS – LPC47M192

Page 219

Rev. 03/30/05

DATASHEET

SMBus Timing

BUF

HD;STA

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

SU;STO

SCLK

SDA

FIGURE 44 – SMBUS TIMING

SYMBOL

PARAMETER

LIMITS

UNITS

COMMENTS

MIN

MAX

FSMB

SMB Operating Frequency

400

kHz

Note 1

TSP

Spike Suppression

Note 2

TBUF

Bus free time between Stop and Start

Condition

1.3

µs

THD:STA

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

0.6

µs

TSU:STA

Repeated Start Condition setup time

0.6

µs

TSU:STO

Stop Condition setup time

0.6

µs

THD:DAT

Data hold time

0.3

0.9

µs

TSU:DAT

Data setup time

100

Note 3

TLOW

Clock low period

1.3

µs

THIGH

Clock high period

0.6

µs

Clock/Data Fall Time

20+0.1Cb

300

Clock/Data Rise Time

20+0.1Cb

300

Capacitive load for each bus line

400

Note 1:

The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified in the System

Management Bus Specification, Rev 1.1. This corresponds to the maximum clock frequency for fast mode

devices on the I

2C bus. See “The I2C Bus Specification,” version 2.0, Dec. 1998.

Note 2:

At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter.

Note 3:

If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (TR max)

+ 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.

LPC47M192 Datasheet(PDF) 219 Page - SMSC Corporation

LPC47M192 Datasheet(HTML) 219 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL