SC16C652B datasheet(27/44 Pages) PHILIPS

27 / 44 page

Philips Semiconductors

SC16C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Product data

Rev. 03 — 10 December 2004

27 of 44

9397 750 14452

[1]

When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

EFR[5]

Special Character Detect.

Logic 0 = Special character detect disabled (normal default condition).

Logic 1 = Special character detect enabled. The SC16C652B compares

each incoming receive character with Xoff2 data. If a match exists, the

received data will be transferred to FIFO and ISR[4] will be set to

indicate detection of special character. Bit-0 in the X-registers

corresponds with the LSB bit for the receive character. When this feature

is enabled, the normal software ﬂow control must be disabled (EFR[3:0]

must be set to a logic 0).

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],

and MCR[7:5] can be modiﬁed and latched. After modifying any bits in the

enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.

This feature prevents existing software from altering or overwriting the

SC16C652B enhanced functions.

Logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4],

and MCR[7:5] are saved to retain the user settings, then IER[7:4]

ISR[5:4], FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible

with SC16C554 mode. (Normal default condition.)

Logic 1 = Enables the enhanced functions. When this bit is set to a

logic 1, all enhanced features of the SC16C652B are enabled and user

settings stored during a reset will be restored.

3:0

EFR[3:0]

Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming

these bits. See Table 24.

Table 24:

Software ﬂow control functions[1]

Cont-3

Cont-2

Cont-1

Cont-0

TX, RX software ﬂow controls

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 23:

Enhanced Feature Register bits description…continued

Bit

Symbol

Description

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