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SC16C652B Datasheet(PDF) 30 Page - NXP Semiconductors |
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SC16C652B Datasheet(HTML) 30 Page - NXP Semiconductors |
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30 / 44 page  Philips Semiconductors SC16C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder Product data Rev. 03 — 10 December 2004 30 of 44 9397 750 14452 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 10. Dynamic characteristics [1] Applies to external clock, crystal oscillator max 24 MHz. Table 29: AC electrical characteristics Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified. Symbol Parameter Conditions 2.5 V 3.3 V 5.0 V Unit Min Max Min Max Min Max t1w, t2w clock pulse duration 10 - 6 - 6 - ns t3w oscillator/clock frequency [1] - 48 - 80 80 MHz t6s address set-up time 0 - 0 - 0 - ns t6h address hold time 0 - 0 - 0 - ns t7d IOR delay from chip select 10 - 10 - 10 - ns t7w IOR strobe width 25 pF load 77 - 26 - 23 - ns t7h chip select hold time from IOR 0 - 0 - 0 - ns t9d read cycle delay 25 pF load 20 - 20 - 20 - ns t12d delay from IOR to data 25 pF load - 77 - 26 - 23 ns t12h data disable time 25 pF load - 15 - 15 - 15 ns t13d IOW delay from chip select 10 - 10 - 10 - ns t13w IOW strobe width 20 - 20 - 15 - ns t13h chip select hold time from IOW0 - 0 - 0 - ns t15d write cycle delay 25 - 25 - 20 - ns t16s data set-up time 20 - 20 - 15 - ns t16h data hold time 15 - 5 - 5 - ns t17d delay from IOW to output 25 pF load - 100 - 33 - 29 ns t18d delay to set interrupt from Modem input 25 pF load - 100 - 24 - 23 ns t19d delay to reset interrupt from IOR 25 pF load - 100 - 24 - 23 ns t20d delay from stop to set interrupt - 1 - 1 - 1 Rclk t21d delay from IOR to reset interrupt 25 pF load - 100 - 29 - 28 ns t22d delay from start to set interrupt - 100 - 45 - 40 ns t23d delay from IOW to transmit start 8 24 8 24 8 24 Rclk t24d delay from IOW to reset interrupt - 100 - 45 - 40 ns t25d delay from stop to set RXRDY- 1 - 1 - 1 Rclk t26d delay from IOR to reset RXRDY - 100 - 45 - 40 ns t27d delay from IOW to set TXRDY - 100 - 45 - 40 ns t28d delay from start to reset TXRDY- 8 - 8 - 8 Rclk tRESET Reset pulse width 200 - 40 - 40 - ns N baud rate divisor 1 216 − 11 216 − 11 216 − 1Rclk |
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