SCD1284 datasheet(157/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

157

8.3

AC Characteristics

8.3.1

Asynchronous Timing

Refer to the Figures 6-1 through 6-7 for the reference numbers in the following table.

Table 27. Asynchronous Timing Reference Parameters (Sheet 1 of 2)

Timing

Number

Figure

Parameter

MIN

MAX

Unit

Figure

RESET* low pulse width

TCLK

Address setup time to CS* or DS*

R/W* setup time to CS* or DS*

Address hold time after CS*

R/W* hold time after CS*

DTACK* low to read data valid

DTACK* low from CS* or DS2

2 TCLK

4 TCLK + 30

Data Bus tristate after CS* or DS* high

CS* or DGRANT* high from DTACK* low

t10

DTACK* inactive from CS* or DGRANT* and DS* high

t11

DS* high pulse width

t12

Write data valid from CS* and DS* low

1TCLK

t13

Write data hold time after DS* high

t14

Clock period (TCLK)1, 3

40.0

1000

t15

Clock low time1

0.3 TCLK

0.7 TCLK

t16

Clock high time1

0.3 TCLK

0.7 TCLK

t17

Propagation delay, DGRANT* and DS* to DPASS*

t18

Setup time, SVCACK* to DS* and DGRANT*

t19

Setup time, DMAACK* to rising edge of CLK

t20

Hold time, read data after rising edge of CLK

t21

Setup time, write data to rising edge of CLK

t22

DTACK* active pull-up time4

see note 4

t23

Data valid after falling edge of CLK (DMA read)

t24

Hold time, DMAREQ* after DMAACK* falling edge,

last DMA cycle

1 CLK

+ 15

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