SCD1284 datasheet(156/176 Pages) INTEL

156 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

156

Datasheet

The signals specific to the parallel port meet all requirements of the IEEE STD 1284 specification,

except for input signal protection (

−2.0 to + 7.0 V); external circuitry is required to meet this

specification.

Note:

While the CD1284 is a highly dependable device, there are a few guidelines to ensure that the

maximum possible level of overall system reliability is achieved. First, design the PC board to

provide maximum isolation of noise. A four-layer board is preferable, but a two-layer board will

work if proper power and ground distribution is implemented. In either case, decoupling capacitors

mounted close to the CD1284 are strongly recommended. Noise typically occurs when either the

CD1284 data bus drivers come out of tristate to drive the bus during a read, or when an external bus

buffer turns on during a write cycle. This noise, a rapid rate-of-change of supply current, causes

‘ground bounce’ in the power-distribution traces. This ground bounce, a rise in the voltage of the

ground pins, effectively raises the input logic thresholds of all devices in the vicinity, resulting in

the possibility of a ‘1’ being interpreted as a ‘0’.

To reduce the possibility of ground-bounce affecting the operation of the CD1284, Intel has

specified the input-high voltage (VIH) of the CLK and RESET* pins at 2.7 V, instead of the TTL-

standard 2.0 V. This eliminates any sensitivity to ground bounce, even in extremely noisy systems.

Although 2.7 V is higher than the industry-standard 2.4-V output (VOH) specified for TTL, there

are several simple ways to meet this specification:

1. Use any of the available advanced-CMOS logic families (FACT, ACL, etc.). These CMOS

output buffers will pull-up close to VCC when not heavily loaded. In addition, AS and ALS

TTL can be used if the output of the TTL device is only driving one or two CMOS loads.

2. As noted in the Texas Instruments ALS/AS Logic Data Book (1986 — pages 4-18 and 4-19),

the VOH output of these families exceeds 3.0 V at low-current loading. Other manufacturers

publish similar data. Intel recommends the use of one of these two options for the CLK input

to ensure fast, clean edges.

Note that RESET* can, if desired, be pulled up passively with

≤ 1-kΩ resistor.

IIL

Input leakage current

−10

µA0 < V

IN < VCC

ILL

Data bus tristate leakage

current

−10

µA0 < V

OUT < VCC

IOC

Open-drain output leakage

current

−10

µA0 < V

OUT < VCC

ICC

Power supply current

CLK = 25 MHz

CIN

Input capacitance

COUT

Output capacitance

NOTES:

1. VIH is 2.7 V minimum on RESET*, CLK, and DMAACK*.

2. VOL for open-drain signals is 0.5 V @ 8 mA sinking because these signals can be wire-OR’ed in some systems and can have

multiple pull-up resistors that increase the load on the output.

(@ VCC = 5V ± 5%, TA = 0°C to 70°C)

Symmetrical input/output drive:

±14 mA

Controlled voltage slew rate: 0.4 V/

µs

Input hysteresis: 0.8 V

SCD1284 Datasheet(PDF) 156 Page - Intel Corporation

SCD1284 Datasheet(HTML) 156 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL