SCD1284 datasheet(153/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

153

7.8.13

Short Pulse Register

This register performs two functions,

• It sets the duration of the short pulse used by the IEEE 1284 protocols for all modes other than

Compatibility;

• In Compatibility mode, it sets the duration of the ACK* pulse.

For non-compatible modes, SPR must be set to n

− 2, where n is the number of CLKs in a 500-ns

pulse. The peripheral host initializes this register with the appropriate value to generate a 500-ns

pulse width based on the operating frequency of the device. In Compatibility mode, SPR should be

set to the needed length of the ACK* pulse. This is provided to enable the device to interface to

Bit

Description

7:5

These read-only bits are always ‘0’.

TestMux: When this bit is set, the state of the state machine is multiplexed onto the GPIO pins for debugging

purposes.

GPIO is not possible when this bit is set.

3:2

Clear Pause and Set Pause: These commands implement an error pause in Compatibility mode. Usually,

errors are presented to the host parallel port by the peripheral during the active BUSY period of a data

transfer. SetPs remains set until ClrPs is set, at which time both clear.

In most cases, the slave host also sets RevRq at the same time when SetPs is set to:

1) Lockup Compatibility mode with BUSY high, and

2) Request a reverse transfer if the master requests that an additional status be sent in the reverse direction

EPP Interrupt Request: This command causes the state machine to generate the EPP interrupt sequence.

This bit clears on the initiation of the Intr (PerClk) pulse on the parallel port interface.

Reverse Request: This command requests that the host parallel port initiate the defined interface reversal

handshake as defined by the IEEE STD 1284 specification. The command bit clears to indicate completion

after the command executes on the interface. For Reverse Nibble and Reverse Byte modes, this occurs after

negotiation is complete; in ECP mode, it occurs after the Reverse Request signal on the parallel port interface

goes low.

In ECP mode, nPeriphRequest (nFault) is driven low to request that the host-side parallel port reverse the

direction of the interface.

When this bit is set upon termination of Compatibility mode, the CD1284 can indicate that reverse data is

available (through the nDataAv signal) immediately upon recognition of a Reverse Nibble or Reverse Byte

negotiation. To obtain this behavior, this bit should be initialized to ‘1’ and set to ‘1’ upon termination of

Compatibility mode.

Access: Read/Write

8-Bit Hex Address: 26

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

8-bit Binary Value

SCD1284 Datasheet(PDF) 153 Page - Intel Corporation

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