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SCD1284 Datasheet(PDF) 150 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 150 Page - Intel Corporation |
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150 / 176 page ![]() CD1284 — IEEE 1284-Compatible Parallel Interface Controller 150 Datasheet Setting the bits in this register enables the CD1284 to generate an interrupt – if SigCh (PCIER[4]) is set – when the selected signal changes from low-to-high (rising edge). Bits 7:4 are reserved and must be written as zeros; they return zero when read. The settings in this register have no effect (that is, a SigCh interrupt is not generated) unless the device is in Manual mode. 7.8.8 Output Value Register This register controls output signals. In Manual mode, all signals are controlled by these register settings. In Compatibility and EPP modes, PerBsy and PerClk are controlled by the internal parallel port state machine, while AkDaRq, xFlag, and nDatAv are controlled by this register. In ECP mode, the settings in this register have no effect. 7.8.9 Parallel Channel Interrupt Enable Register 7.8.10 Parallel Channel Interrupt Status Register Register Name: OVR Register Description: Output Value Access: Write only 8-Bit Hex Address: 2B Default Value: 48 Bit 7Bit 6Bit 5Bit 4Bit 3 Bit 2Bit 1 Bit 0 PerBsy PerClk AkDaRq xFlag nDatAv 0 0 0 Bit Description 7:6 Peripheral Busy and Peripheral Clock: User-controlled in Manual mode only. 5 Acknowledge Data Request: In Compatible mode, this signal is the PError (Peripheral Error) signal. In EPP mode, this signal is auxiliary and is a user-defined signal (USER 1). 4 XFlag: In Compatible mode, this signal is the SELCT (Select) signal. In EPP mode, this signal is auxiliary and is a user-defined signal (USER 2). 3 Negative-true Data Available: In Compatible mode, this signal is the nFault (negative-true fault) signal. In EPP mode, this signal is auxiliary and is a user-defined signal (USER 3). 2:0 Reserved: These bits must be written as ‘0’. Register Name: PCIER Register Description: Parallel Channel Interrupt Enable Access: Read/Write 8-Bit Hex Address: 22 Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 21 Bit Bit 0 TimEn NegCh SigCh EPPAW DirCh IDReq nINIT Register Name: PCISR Register Description: Parallel Channel Interrupt Status Access: Read/Write 8-Bit Hex Address: 23 Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 TimOvr NegCh SigCh EPPAW DirCh IDReq nINIT |
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