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SCD1284 Datasheet(PDF) 146 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 146 Page - Intel Corporation |
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146 / 176 page ![]() CD1284 — IEEE 1284-Compatible Parallel Interface Controller 146 Datasheet The SDTPR is cleared by a device reset. 7.8 Channel Registers — Parallel Port 7.8.1 EPP Address Register This register is only used during EPP mode. The CD1284 deposits the value obtained during an EPP address write command in this register. The CD1284 provides this value in response to an EPP address read command. 7.8.2 Host Timeout Value Register This register holds the 8-bit value used to set the Host timeout period. The HTVR is an unsigned, binary value. The reset state of this register is ‘0xFF’. A function missing in Revision C and earlier devices is an on-chip timer to indicate that the remote host has not responded in a specified time period. The Host timeout is defined in the IEEE STD 1284 specification as a period of one second. Revision D and newer devices add a user-programmable timer to provide a timeout if the remote host does not respond to specific parallel port transactions. The timer is started by the parallel port state machine each time it starts a sequence requiring a host response. Activation of the timer is automatic and an interrupt is generated to the local host CPU if the timer expires before the remote host responds. Note: Users familiar with the IEEE specification note that the events that start the timer cause the peripheral device to wait for a remote host-generated event. For example, during the negotiation sequence after event 2, the peripheral waits for event 3 – a host-generated event. If the host does not respond and moves the negotiation sequence to event 4 within one second, the peripheral enters the ‘host timeout’ condition. The timer is a 14-bit counter clocked by the system clock (CLK) prescaled (divided) by 2048. Then the 8-bit HTVR (address offset 0x24) is programmed and compared with the most-significant 8 bits of the 14-bit counter. Each time the parallel port executes an event requiring a host response, the Register Name: EAR Register Description: EPP Address Access: Read/Write 8-Bit Hex Address: 25 Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8-bit Binary Value Register Name: HTVR Register Description: Host Timeout Value Access: Read/Write 8-Bit Hex Address: 24 Default Value: FF Bit 7Bit 6Bit 5Bit 4Bit 3 Bit 2Bit 1 Bit 0 HTVR[7] HTVR[6] HTVR[5] HTVR[4] HTVR[3] HTVR[2] HTVR[1] HTVR[0] |
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