SCD1284 datasheet(143/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

143

These registers are cleared by a device or FIFO reset and marked as empty in HRSR. Any tagged

status is also cleared.

7.7.13

Parallel FIFO Quantity Register

This register maintains the quantity (or count) of either data bytes or space available in the parallel

FIFO. In the receive direction (DMAdir

= 0), PFQR counts data characters in the FIFO. In the

transmit direction (DMAdir

= 1), PFQR counts space available in the FIFO for additional

characters to transmit. FIFOres, together with the value of DMAdir, initialize PFQR to either x’00

(receive) or x’40 (transmit).

In either case, the PFQR indicates only the quantity of data or space available in the FIFO, and

does not include the data pipeline registers.

7.7.14

Parallel FIFO Status Register

This read-only register provides the current FIFO and data pipeline status. Host software should

examine these bits in response to pipeline interrupts or polling operations.

This register is not directly cleared by reset, but the individual bits reflect the status of other

registers.

Access: Read/Write

8-Bit Hex Address: 3A

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Data or Space Available in FIFO — Max 0x40

Access: Read only

8-Bit Hex Address: 32

Default Value: 40

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FFfull

FFempty

Timeout

HRtag

HRdata

Stale

OneChar

DataErr

Bit

Description

Parallel FIFO is Full: If this bit is set, it indicates that the parallel FIFO is full.

Parallel FIFO is Empty: If this bit is set, the parallel FIFO is empty.

Timeout: This bit is set when Stale goes from false to true. In the receive direction, Timeout is delayed until

the FIFO is empty and all DMA cycles are complete (PFHR2 may or may not be full). Timeout is a pipeline

interrupt condition and must be cleared manually by the CPU. This is done by toggling ClrTO (PACR[3]) or by

a FIFO reset in PFCR.

Holding Register Tag: This bit indicates that a tagged character is in either PFHR1, PFHR2, or both. If

enabled, this bit being set causes a host interrupt to be generated. The host should examine the HRSR to

determine the exact cause(s) of this bit being set.

Holding Register Data: If this bit is set, it indicates that either PFHR1, PFHR2, or both contain data.

SCD1284 Datasheet(PDF) 143 Page - Intel Corporation

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