SCD1284 datasheet(144/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

144

Datasheet

7.7.15

Parallel FIFO Threshold Register

This register sets the FIFO threshold for initiating DMA requests for data transfer. The value is

expressed in bytes. Whenever DMAen is true, regular comparisons are made between the PFQR

and the PFTR. If the value in the PFQR is greater than or equal to the threshold, the DMA request

logic becomes active and remains active until the FIFO is essentially filled or emptied. An odd

character or space in the FIFO can remain.

In the receive direction, the Holding register pipeline (PFHR1 and PFHR2) are kept filled, so that

tagged data (for example, ECP mode addresses) can be detected and passed to the host by an

interrupt. For example, if the FIFO and data pipeline are initialized for receive, and 40 hex bytes

are placed into the FIFO from the parallel port, the first two of those bytes automatically are placed

in the Pipeline registers. If the PFTR were programmed to x’40 bytes, x’42 bytes must arrive to

trigger a DMA transfer.

PFTR is cleared by device reset; it is not cleared by FIFOres.

7.7.16

Run Length Count Register

This register works with the Holding registers (PFHR1 and PFHR2) to perform run-length

encoding and decoding when RLEen is set (PFCR[3]). The parallel port must be in ECP mode; in

other modes, run-length encoding does not occur.

Stale: This bit is set when the stale data timer expires (see the description of SDTPR). If a single byte

remains in the data pipeline when this bit is set, a host interrupt is generated, the OneChar bit is set, and new

data entering the FIFO does not move into PFHR1 until PFHR2 empties. If two or more bytes remain in the

pipeline when this bit is set, a host interrupt is not generated, however, a DMA request is generated if

enabled.

One Character: In the receive direction, this bit set indicates that the FIFO is empty and stale, and one

character remains in PFHR2. This condition occurs if an odd number of bytes is transferred by the parallel

interface. Since DMA cycles only move even numbers of bytes (words) and odd transfers leave one byte

remaining, host software must remove this character outside of DMA transfer cycles.

Data Error: If this bit is set, it indicates that one or more of the bits in the DER are set.

Access: Read/Write

8-Bit Hex Address: 3B

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMA Transfer Threshold

Bit

Description (Continued)

Access: Read/Write

8-Bit Hex Address: 37

Default Value: 00

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

7-bit Unsigned Binary Count

SCD1284 Datasheet(PDF) 144 Page - Intel Corporation

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