SCD1284 datasheet(140/176 Pages) INTEL

140 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

140

Datasheet

7.7.7

Parallel Channel Reset Register

This register exists only in the Channel 0 register set and is in the equivalent address location as the

MSVR register of the serial channels.

7.7.8

Parallel FIFO Control Register

This register controls overall function of the parallel FIFO. These functions include resetting

(flushing) the FIFO, enabling DMA transfers, enabling host interrupts, run-length encoding, and so

on. The host sets these bits according to the mode of operation required.

After hard reset (RESET* or a CCR command of x’81 in one of the two serial channels), this

Reserved: Must be ‘0.’

AsyncDMA: AsyncDMA causes the device to synchronize the DMAACK* signal to the internal clock (rising

clock edge). This capability provides an asynchronous DMA interface for systems that cannot meet the set-up

times required by the synchronous DMA logic.

Refer to Chapter 8.0 for specific timing relationships between CLK and DMAACK* when AsyncDMA is

enabled.

Unfair: This bit overrides the Fair Share function of the device. If this bit is set, the device posts service

requests even if the service request is already asserted by an external device. The override is in effect for

channels 2 and 3; Fair Share is not functional on the parallel service request.

For applications where the three serial channel service request outputs are wire-OR’ed together, set Unfair so

that an interrupt of one type does not prevent posting one of the other types (receive, transmit, and modem).

Access: Read/Write

8-Bit Hex Address: 6C

Default Value: 00

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

000

0000

PChReset

Bit

Description

Bit

Description

7:1

Reserved: Must be ‘0’

PChReset: Setting this bit asserts the equivalent of a hardware power-on reset to the parallel channel,

channel 0. If set by the host, it must be cleared to resume normal parallel channel operation. This hardware

reset affects only the parallel channel and has no affect on other functions of the device.

Access: Read/Write

8-Bit Hex Address: 31

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

FIFOres

DMAen

DMAdir

IntEn

RLEen

setTAG

ErrEn

DMAbufWe

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