SCD1284 datasheet(137/176 Pages) INTEL

137 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

137

7.7.2

DMA Buffer Data Register — High

7.7.3

DMA Buffer Data Register — Low

This 16-bit data register is used to buffer DMA data transfers to and from the CD1284. Under

normal operating conditions, this register is only accessed during a DMA data transfer cycle. If the

DMAbufWe (PFCR[0]) is set to ‘1’ and DMAdir (PFCR[5]) is set to ‘1’, data may be transferred

from the host to the FIFO by directly writing to the DMABUF. The data automatically moves

forward into the FIFO through the Data Pipeline Holding registers. The user must ensure that the

FIFO has sufficient free space to accept the data before writing into the DMABUF.

The BYTESWAP pin determines the order of byte transfer from this register into the data pipeline.

If BYTESWAP is set to ‘1’, data transferred on DB[15:8] is the first byte transferred into the data

pipeline and DB[7:0] is transferred second. If BYTESWAP is set to ‘0’ this sequence is reversed.

The same applies during data read during DMA transfers: if BYTESWAP is set to ‘1’, data from

the data pipeline moves to the upper byte of DMABUF, the next byte moves into the lower byte.

Again, if BYTESWAP is set to ‘0’, this sequence is reversed.

Bit

Description

DMA Write Error: This bit is set if the DMA control logic has written to the DMA buffer when it already

contains data. It indicates that an invalid DMA transfer cycle occurred (a DMAACK* without a corresponding

DMAREQ*).

DMA Read Error: As with bit 7, this bit indicates that DMA logic has performed a read from the DMA buffer

when there was no data in it. It indicates that an invalid DMA transfer cycle occurred.

Buffer Write Error: This bit indicates that a system write to the DMA buffer occurred while it still contained

data.

Buffer Read Error: This bit indicates that a system read from the DMA buffer occurred while it was empty.

Holding Register 1 Write Error: This bit indicates that a system write to PFHR1 occurred while it still

contained data.

Holding Register 1 Read Error: This bit indicates that a system read from PFHR1 occurred while it was

empty.

Holding Register 2 Write Error: This bit indicates that a system write to PFHR2 occurred while it still

contained data.

Holding Register 2 Read Error: This bit indicates that a system read from PFHR2 occurred while it was

empty.

Access: Read/Write

8-Bit Hex Address: 30

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Access: Read/Write

8-Bit Hex Address: 30

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCD1284 Datasheet(PDF) 137 Page - Intel Corporation

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