SCD1284 datasheet(135/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

135

7.6.8

Serial Service Request Enable Register

This register enables the conditions that cause the CD1284, to post a service request by the SVRR

and the SVCREQ* output pins, and applies to the serial channels only. Each of the individual

enable bits control one type of service request.

7.6.9

Transmit Baud Rate Period Register

This register holds the baud rate divisor for the transmitter and is used in conjunction with the

TCOR. This provides the clock, which is divided by this value. The time period produced must

equal the value for one bit time of the transmit data.

Access: Read/Write

8-Bit Hex Address: 06

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MdmChg

RxData

TxRdy

TxEmpty

NNDT

Bit

Description

Modem Change: This bit enables the Modem Change service request. When this bit is ‘1’, any selected

modem signal change conditions (as programmed by MCOR1 and MCOR2) cause a modem service request

to be posted.

6:5

These bits must always be ‘0’.

Receive Data Enable: This bit enables the posting of receive service requests when characters have been

received and either the FIFO reaches the programmed threshold (set by COR3) or the receive timeout period

has expired.

This bit must always be ‘0’.

2:1

Transmitter Ready and Transmitter Empty: The transmitter can be enabled to post service requests on one

of two conditions: either the FIFO is empty or the Transmitter Shift register is empty.

TxRdy enables the service request on the condition that the FIFO is empty. In this case, there are still two

characters available for transmission before the transmitter underruns (one in the Shift register and one in the

Holding register).

TxEmpty enables the service request on the condition that the Shift register is empty. The transmitter

underruns due to the latency experienced between the time the service request is posted and the time the

host can load the FIFO. Under normal operating conditions, TxEmpty is set and TxRdy reset when there is no

more data to transmit and the host requires notification that the last character was sent before it can disable

the transmitter.

No New Data Timeout Enable: This bit activates the optional exception service request when all data is

removed from the FIFO and no new data has arrived after a preprogrammed delay period set by the value in

the RTPR. The LIVR (or RIVR) indicates a receive exception in the IT2–IT0 vector bits. There is no data

associated with this exception service request. RDSR[7] indicates that the service request is for an NNDT

condition.

Access: Read/Write

8-Bit Hex Address: 72

Default Value: 41

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2

Bit 1

Bit 0

Binary Divisor Value

SCD1284 Datasheet(PDF) 135 Page - Intel Corporation

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