SCD1284 datasheet(131/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

131

7.5.4

Modem Signal Value Register 2

MSVR1 and MSVR2 provide information regarding the state of the modem input pins (DSR*,

CTS*, RI*, and CD*) and allows control of the modem output pins (DTR* and RTS*). A write to

any of the input bits has no effect. With the exception of the least-significant two bits, the registers

reflect identical data. The two are provided as a convenience for control of the modem output pins.

It is not necessary for host software to keep a copy of the current state of either when controlling

the other. The actual signal level on the output is the inverse of the value placed in this register. For

example, setting the DTR bit causes the DTR output to become active-low. The state of the modem

input pins is also the inverse of the value in the corresponding bit in the registers.

7.5.5

Receive Baud Rate Period Register

This register holds the baud rate divisor for the receiver. It is used in conjunction with the RCOR.

This provides the clock, which is divided by this value. The time period produced must equal the

value for one bit time of the receive data.

7.5.6

Receive Clock Option Register

The RCOR selects the clock source, which drives the RBPR. The value in ClkSel2–ClkSel0 selects

one of five possible clocks generated from the master clock (CLK).

Access: Read/Write

8-Bit Hex Address: 6D

Default Value: XX

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

DSR

CTS

DTR

Access: Read/Write

8-Bit Hex Address: 78

Default Value: 41

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Binary Divisor Value

Access: Read/Write

8-Bit Hex Address: 7C

Default Value: 01

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

ClkSel2

ClkSel1

ClkSel0

ClkSel2

ClkSel1

ClkSel0

Clock Selected

Clk0 (CLK

÷ 8)

Clk1 (CLK

÷ 32)

Clk2 (CLK

÷ 128)

Clk3 (CLK

÷ 512)

Clk4 (CLK

÷ 2048)

SCD1284 Datasheet(PDF) 131 Page - Intel Corporation

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