SCD1284 datasheet(130/176 Pages) INTEL

130 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

130

Datasheet

7.5.2

Modem Change Option Register 2

7.5.3

Modem Signal Value Register 1

Bit

Description

7:4

DSRzd, CTSzd, RIzd and CDzd: Each of these bits controls its corresponding input pin. If the bit is set, the

function is enabled and transitions from one-to-zero (zeros detect) generate an SVCREQM* service request.

3:0

DTRth3 through DTRth0: These bits form a binary value to determine when the DTR output is negated

(based on the number of characters in the receive FIFO). When the FIFO holds more characters than this

value, DTR is negated, informing the remote to stop transmission. This value must be set to a value

numerically larger than the value set for the receive FIFO threshold in COR3.

Access: Read/Write

8-Bit Hex Address: 16

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

DSRod

CTSod

RIod

CDod

Bit

Description

7:4

DSRod, CTSod, RIod, CDod: Each of these bits controls its corresponding input pin. If the bit is set, the

function is enabled and transitions from ‘0’-to-‘1’ (ones detect) generate an SVCREQM* service request.

3:0

These bits are not used and must be ‘0’.

Access: Read/Write

8-Bit Hex Address: 6C

Default Value: XX

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

DSR

CTS

RTS

DTRth3

DTRth2

DTRth1

DTRth0

Number of Characters in FIFO

Automatic DTR mode disabled.

1 character

2 characters

•••

•

11 characters

12 characters

110

Not used.

111

SCD1284 Datasheet(PDF) 130 Page - Intel Corporation

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