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SCD1284 Datasheet(PDF) 132 Page - Intel Corporation |
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SCD1284 Datasheet(HTML) 132 Page - Intel Corporation |
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132 / 176 page ![]() CD1284 — IEEE 1284-Compatible Parallel Interface Controller 132 Datasheet 7.5.7 Received Data Count Register The RDCR indicates the number of good characters currently in the serial received data FIFO. Host software can use this value as a loop counter when taking characters out of the FIFO. The value in this register is only valid during the context of a service request acknowledge. At other times, it may or may not give a true indication of the number of characters in the FIFO. 1 0 1 Not used. 1 1 0 1 1 1 Register Name: RDCR Register Description: Received Data Count Access: Read only 8-Bit Hex Address: 0E Default Value: 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 CT3 CT2 CT1 CT0 ClkSel2 ClkSel1 ClkSel0 Clock Selected Bit Description 7:4 These bits must always be ‘0’. 3:0 Character Count 3:0: The encoding for these bits is: CT3 CT2 CT1 CT0 Number of characters in FIFO 0 0 0 0 Not used. 0 0 0 1 1 character 0 0 1 0 2 characters •• •• 1 0 1 1 11 characters 1 1 0 0 12 characters 110 1 Not used. 111 0 111 1 |
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