SCD1284 datasheet(139/176 Pages) INTEL

139 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

139

7.7.6

Parallel Auxiliary Control Register

This register provides some special functions for the parallel data path and interrupt generation

circuitry. The upper two bits change the basic timing of the timers associated with the data pipeline.

Bit 5 can disable the stale data timer. Bit 0 overrides the Fair Share functions of the device (serial

and parallel channels).

Bits

Description

7:3

User-defined Interrupt Vector: Host software can use these five bits for any purpose appropriate to the

application. In some cases, these bits might define the rest of a complete interrupt response vector (Motorola-

type systems). In the case of daisy-chain systems made up of multiple CD1284s, these bits define the device

number in the chain.

2:0

Interrupt Vector Type Code: These bits are read/writable in the normal context. These bits are ‘don’t cares’.

Access: Read/Write

8-Bit Hex Address: 3F

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ShrtTen

ShrtStal

StaleOff

FIFOlock

ClearTO

AsyncDMA

Unfair

Bit

Description

ShrtTen: This function shortens the Prescaler count cycle that generates the internal 10-

µs (based on a 25-

MHz system clock) clock for the stale data counter. This bit is cleared by RESET*. If set, the 10-

µs ‘ticks’ of

the counter are generated every two CLKs; the normal period is one ‘tick’ every 250 CLKs.

ShrtStal: This function shortens the period of the stale data timer. The stale data timer includes a divide-by-

10 prescaler; setting this bit bypasses the prescaler function thus causing the stale data timer to count on

each 10-

µs clock ‘tick’.

If both ShrtTen and ShrtStal are set, the stale data timer counts on every other CLK.

StaleOff: If set, this bit masks off the Stale Status bit. The inverse of this bit is AND’ed with the stale state

condition of the parallel channel to produce the stale status and disables OneChar and Stale as interrupt

sources. StaleOff is provided primarily for test and development purposes if slow movement of data into the

parallel port causes Stale and OneChar to always appear true.

FIFOlock: The FIFOlock bit causes the FIFO to stop accepting data from the parallel channel state machine.

This action makes the FIFO appear full to the parallel port, thus causing it to enter the ‘busy’ state. This

function is primarily intended for use in system testing to cause a timeout on the 1284 bus.

Setting this bit in ECP Forward mode may cause a stall condition event 35 because event 36 does not occur

until FIFOlock is cleared. The ECP mode host transfer recovery handshake sequence (from event 35 stall) is

supported and the byte transit discarded as required by the specification. This bit does not provide an

effective means to flow control the host.

Clear Timeout: This bit is a reset bit for the timeout status latch logic. When toggled by software, the timeout

status in the PFSR is cleared; it may be left set to disable the Timeout status function. Note that if this bit is

left set, the OneChar interrupt condition will never become true because the OneChar interrupt logic uses the

timeout status to determine when the FIFO has become stale.

SCD1284 Datasheet(PDF) 139 Page - Intel Corporation

SCD1284 Datasheet(HTML) 139 Page - Intel Corporation

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