SCD1284 datasheet(138/176 Pages) INTEL

138 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

138

Datasheet

These resisters can be read through DMA acknowledge or PIO cycles, however, the DMABUF

registers can only be read when the DMAREQ* signal is active. If DMAREQ* is inactive, the

DMABUF registers will be empty. DMAfull (HRSR[3]) indicates if the DMABUF register is

empty when DMAREQ* is active.

7.7.4

Firmware Revision Code Holding Register Status Register

The HRSR is a read-only register that indicates current data pipeline status. This register is not

directly set to any particular value by a device reset, but reflects the current state of bits in other

registers.

7.7.5

Local Interrupt Vector Register

This read/write register can be initialized to any desired value and, when read in the normal context

(that is, not a service acknowledge context), the same value will be returned. The upper 5 bits are

copied into the appropriate vector register (MIVR, PIVR, TIVR, or RIVR) when the corresponding

SVCACK* signal is activated and an SVCREQ* of the same type is active. During this hardware-

activated service acknowledge read cycle, the appropriate vector register (MIVR, PIVR, TIVR, or

RIVR) is driven onto the data bus, DB[7:0].

Access: Read only

8-Bit Hex Address: 34

Default Value: 04

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HR1full

HR1tag

HR2full

HR2tag

DMAfull

DMAmpty

DMAact

Ctnot0

Bit

Description

7:6

Holding Register 1 Full and Holding Register 1 Tagged: These two bits indicate status of PFHR1. Bit 7

indicates that the register contains data; bit 6 indicates that the data is tagged. Bits 7 and 6 can be set

simultaneously.

5:4

Holding Register 2 Full and Holding Register 2 Tagged: These two bits indicate status of PFHR2. Bit 5

indicates that the register contains data; bit 4 indicates that the data is tagged. Bits 5 and 4 can be set

simultaneously.

3:2

DMA Buffer Full and DMA Buffer Empty: These two bits indicate status of the DMA transfer buffer (DMA

buffer). Bit 3 indicates that the register contains data; bit 2 indicates that it is empty.

DMA Active: When this bit is set, it indicates that the DMA handshake is active and a DMA service has been

requested but is not yet complete (DMAREQ* active – waiting for DMAACK*).

Count Not Zero: This bit indicates that the RLE counter is not zero, thus run-length encoding/decoding is in

progress.

Access: Read/Write

8-Bit Hex Address: 18

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

User-Defined Bits

IT2

IT1

IT0

SCD1284 Datasheet(PDF) 138 Page - Intel Corporation

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