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SCD1284 Datasheet(PDF) 149 Page - Intel Corporation

Part # SCD1284
Description  IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
PDF  176 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

SCD1284 Datasheet(HTML) 149 Page - Intel Corporation

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IEEE 1284-Compatible Parallel Interface Controller — CD1284
Datasheet
149
Any change in the mode of the parallel port is reported to the peripheral host by interrupt if the
NegCh bit (PCIER[5]) is set; host software then reads the NSR to determine the current status and
condition. Once the host has read the NSR status resulting from the current negotiation, it should
clear the register in preparation for additional negotiation cycles. The NSR can be cleared by
writing any value.
7.8.7
Ones Detect Register
Bit
Description
7
Negotiation OK: The state of this bit indicates that the negotiation was successful.
6
Negotiation Failed: The state of this bit indicates that the negotiation failed. The result code indicates which
mode was attempted
5
Host Timeout: This bit indicates that a host timeout occurred on the parallel channel. The accompanying 4-
bit result code indicates that the link has returned to Compatibility mode (x02). See the description of HTVR in
Section 7.8.2 on page 146.
4
Immediate Termination: This bit indicates that the A1284 signal has unexpectedly gone inactive as a result
of an immediate termination from the host and the interface and has reentered Compatibility mode. The 4-bit
negotiation result code should indicate which mode was terminated.
3:0
The lower 4 bits of this register contain a result code that shows the current mode. The following table shows
the encoding of the result code.
0
0
0
0
Compatible mode — no negotiation.
0
0
0
1
Failed negotiation.
0
0
1
0
Compatible mode — termination of a 1284 mode.
001
1
Reserved.
010
0
010
1
011
0
EPP mode.
0
1
1
1
Reserved.
1
0
0
0
Reverse Nibble mode.
1
0
0
1
Reverse Nibble mode — ID request.
1
0
1
0
Reverse Byte mode.
1
0
1
1
Reverse Byte mode — ID request.
1
1
0
0
ECP mode without RLE.
1
1
0
1
ECP mode without RLE — ID request.
1
1
1
0
ECP mode with RLE.
1
1
1
1
ECP mode with RLE — ID request.
Register Name: ODR
Register Description: Ones Detect
Access: Read/Write
8-Bit Hex Address: 2D
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
A1284
nInit
HstBsy
HstClk



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