SCD1284 datasheet(151/176 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

151

PCIER and PCISR provide control and status of interrupts generated by the parallel channel

control state machine. They have the same bit definitions. Each bit in the PCIER enables the

interrupt of the same type in the PCISR. A write of any value to the PCISR in response to an

interrupt request causes it to clear and the interrupt request is removed.

7.8.11

Parallel Configuration Register

This register controls the overall configuration of the parallel port, each of which is described in

IEEE 1284 format below.

Bit

Description

This bit must always be ‘0’

Timer Enable and Timer Over: These two bits are for factory test purposes only and should never be

written.

Negotiation Change: The state of this bit indicates that a change occurred in the negotiation status of the

port. The NSR indicates the new status of the parallel port.

Signal Change Enable: This enable instructs the parallel port to generate an interrupt when any of the

signals specified by the ZDR or ODR change state as programmed. This interrupt is only generated during

Manual mode, however, it cannot be cleared by terminating Manual mode.

EPPAW: The state of this bit indicates that the remote master has written an EPP address to the CD1284.

The new EPP address value is placed in the EAR.

Direction Change: This bit indicates that the host-side parallel port changed the direction of the interface.

Generally, this is in response to a request made by the CD1284 through the RevRq bit (SCR[0]). DirCh

indicates that the direction was reversed through the defined protocol and the CD1284 can now send data to

the master.

ID Request: The state of this bit indicates that the host has requested that the CD1284 send its ID data

string. The peripheral host sends the appropriate ID string (this is application dependent).

nINIT: This interrupt is generated when an nINIT pulse is received while in Compatibility mode. The interrupt

occurs on the leading edge of the nINIT pulse.

Access: R/W

8-Bit Hex Address: 20

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ManMd

E1284

ETxfr

Ig_SEL

HTmrTst[1]

HTmrTst[0]

MMDir

ManOE

SCD1284 Datasheet(PDF) 151 Page - Intel Corporation

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