ADV7311 datasheet(72/84 Pages) AD

72 / 84 page

REV. A

–72–

ADV7310/ADV7311

Mode 3—Master/Slave Option

(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7310/ADV7311 accept or generate horizon-

tal sync and odd/even field signals. A transition of the field input

when

HSYNC is high indicates a new frame, i.e., vertical retrace.

The

BLANK signal is optional. When the BLANK input is dis-

abled, the ADV7310/ADV7311 automatically blank all normally

blank lines as per CCIR-624.

HSYNC is output in master mode

and input in slave mode on

S_VSYNC, BLANK on S_BLANK,

and

VSYNC on S_VSYNC.

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

1234

678

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

Figure 89. SD Timing Mode 3 (NTSC)

622

623

624

625

1234

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

320

Figure 90. SD Timing Mode 3 (PAL)

ADV7311 Datasheet(PDF) 72 Page - Analog Devices

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