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ADV7311 Datasheet(PDF) 24 Page - Analog Devices |
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ADV7311 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 84 page ![]() REV. A –24– ADV7310/ADV7311 SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values 3Eh Reserved 00h 3Fh Reserved 00h 40h SD Mode Register 0 00 NTSC 00h 01 PAL B, D, G, H, I 10 PAL M 11 PAL N 00 0 LPF NTSC 00 1 LPF PAL 01 0 Notch NTSC 01 1 Notch PAL 10 0 SSAF Luma 10 1 Luma CIF 11 0 Luma QCIF 11 1 Reserved 00 0 1.3 MHz 00 1 0.65 MHz 01 0 1.0 MHz 01 1 2.0 MHz 10 0 Reserved 10 1 Chroma CIF 11 0 Chroma QCIF 11 1 3.0 MHz 41h Reserved 00h 42h SD Mode Register 1 SD PrPb SSAF 0 Disabled 08h 1 Enabled SD DAC Output 1 0 1 SD DAC Output 2 0 1 SD Pedestal 0 Disabled 1 Enabled SD Square Pixel 0 Disabled 1 Enabled SD VCR FF/RW Sync 0 Disabled 1 Enabled SD Pixel Data Valid 0 Disabled 1 Enabled 0 Disabled 1 Enabled 43h SD Mode Register 2 SD Pedestal YPrPb Output 0 No pedestal on YUV 00h 1 7.5 IRE pedestal on YUV SD Output Levels Y 0 Y = 700 mV/300 mV 1Y = 714 mV/286 mV SD Output Levels PrPb 0 0 700 mV p-p[PAL]; 1000 mV p-p[NTSC] 01 700 mV p-p 10 1000 mV p-p 11 648 mV p-p SD VBI Open 0 Disabled 1 Enabled SD CC Field Control 0 0 CC disabled 01 CC on odd field only 10 CC on odd field only 11 CC on both fields Reserved 1 Reserved Refer to output configuration section Refer to output configuration section SD SAV/EAV Step Edge Control SD Standard SD Luma Filter SD Chroma Filter |
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