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FM8PC71AM Datasheet(PDF) 29 Page - Feeling Technology Corp. |
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FM8PC71AM Datasheet(HTML) 29 Page - Feeling Technology Corp. |
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29 / 73 page ![]() FM8PC71AM This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. P.29 R1.1.004, Aug 7, 2017 FM8PC71AM 遠翔科技 Feeling Technology 【4】Clock Control The MCU operation frequency rang is as following: ( Fcpu is MCU clock) (1) VDD > 2.0 V Fcpu ≦ 16Mhz (Note: When MCU is Power on, the Fcpu is set 1/2/4/8 Mhz by configuration selection. When MCU is after power on reset, the Fcpu can be switch to 16Mhz by program.) Address 13H: Clock configuration (CLKCFG) Bits 7 6 5 4 3 2 1 0 Name SELCLK[2:0] CLKSW SIRCEN INCODS EXOSEN IRCEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 1 Bit[7:5] : SELCLK[2:0] Select MCU switch-clock. (FIRC=16Mhz) SELCLK[2:0] Select clock(Fsel) 3’b000 (FOSC or FIRC)/1 3’b001 (FOSC or FIRC)/2 3’b010 (FOSC or FIRC)/4 3’b011 (FOSC or FIRC)/8 3’b100 (FOSC or FIRC)/16 3’b101 FSIRC Bit[4] : CLKSW CPU clock switch signal 1 = CPU clock start to switch from Ffig clock to Fsel clock. 0 = CPU clock start to switch from Fsel clock to Ffig clock. Note: If ATSW bit is ‘1’, and LVDTA bit is ‘0’, the CPU clock will be forced to Ffig. Bit[3] : SIRCEN Slow IRC Enable 1 = Enable SIRC. 0 = Disable SIRC. Bit[2] : INCODS Internal clock output disable. 1 = Disable internal IRC clock output. 0 = Enable internal IRC clock output. The IRC clock is driven output to XOUT pin. Bit[1] : EXOSEN External Oscillator Enable. 1 = Enable the external oscillator. The Fcpu clock is switch to external clock(Fosc) from FIRC clock. 0 = Disable Oscillator Enable. Bit[0] : IRCEN Internal clock enable. 1 = Enable internal clock 0 = Disable internal clock. |
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