FM8PC71AM datasheet(27/73 Pages) FEELING

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FM8PC71AM

This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

P.27

R1.1.004, Aug 7, 2017

FM8PC71AM

遠翔科技

Feeling Technology

【3】Power and Reset Management

There are Four cases of reset on MCU controller chip. These cases of reset occurrence are listed below.

1. Power On/Down Reset (normal mode)

POR (VDD

≤ 2.1V), PDR (VDD ≤ 1.8V)

2. Brown out reset

LVDT20 (VDD

≤ LVR1 ==2.0V for > 100ns)

LVDT24 (VDD

≤ LVR2 ==2.4V for > 100ns)

LVDT36 (VDD

≤ LVR3 ==3.6V for > 100ns)

3. Watchdog Reset

WDR (Watch Dog time out)

4. External Reset

EXTR (External Reset PA[2] Low active)

5. Power down Reset (sleep mode)

PDRS (VDD

≤ 1.3V)

If the POR, PDR, PDRS, WDR, LVDT20, LVDT24, EXR or PDRS occurs, the chip will enter reset status. The

following events take place on reset status.

All registers are reset to their default values expect status registers.

The status register (03h) is reset to their default value only for POR/PDR.

After reset status, program counter begins at address 0x0000

PORN is asserted when VDD voltage to the device is upper approximately 2.4V (see Figure 3.0-1).

Address 12H: Power Control Register (PCON)

Bits

Name

SUSPD

GRN_MD

LVDIS

RSTSL[1:0]

LVDT36

LVDT24

LVDT20

Read/Write

R/W

Default

Bit][7] : SUSPD

F/W force system to go into suspend mode.

1 = Suspend mode.

0 = The other operation mode.

Bit][6:5] : GRN_MD,LVDIS

{GRN_MD,LVDIS} Description

2’b00

Normal Mode(SUSPEND=0), and All LVD36, LVDT20, LVDT24 circuit are enable

2’b01

First switch Fcpu clock is Fsirc.

Slow Mode(SUSPEND=0), and All LVD36, LVDT20, LVDT24 circuit are disable

Fcpu enable (Fcpu = Fsirc),

2’b10

Green Mode(SUSPEND=0), and All LVD36, LVDT20, LVDT24 circuit are enable

Fcpu Disable.

2’b11

Green Mode(SUSPEND=0), and All LVD36, LVDT20, LVDT24 circuit are disable

Fcpu Disable.

Bit[4:3] : RSTSL[1:0]*

RSTSL[1:0]

Description

2’b00

POR, WDR can reset system chip.

2’b01

POR, WDR, LVDT2.0 (VDD<= 2.0V) can reset system chip

2’b10

POR, WDR, LVDT24 (VDD<= 2.4V) can reset system chip

2’b11

POR, WDR, EXR can reset system chip.

*POR, PDR, PDRS occurs, the RSTSL[1:0] bits can be reset to default value.

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