FM8PC71AM datasheet(18/73 Pages) FEELING

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FM8PC71AM

This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

P.18

R1.1.004, Aug 7, 2017

FM8PC71AM

遠翔科技

Feeling Technology

2.3 Status Register

This register contains the arithmetic status of the ALU, the RESET status.

If the STAUTS Register the destination for an instruction the affects the Z, DC or C bits, then the write to these three

bits disabled. These bits are set or cleared according to the logic. Furthermore, the /TO and /PD bits are not writable.

Address 03H: Status Register(STATUS)

Bits

Name

Revered

/TO

/PD

Read/Write R

R/W

Default

Bit[4] : /TO

WDT overflow flag bit.

1 = After power on or by the CLRWDT or SLEEP instruction.

0 = A watch-dog time overflow.

Bit[3] : /PD

Power down flag flag.

1 = After power on or by the CLRWDT instruction.

0 = By the SLEEP instruction.

Bit[2] : Z

Zero flag

1 = The result of a logic operation is zero.

0 = The result of a logic operation is not zero.

Bit[1] : DC

Auxiliary carry flag or borrow flag

ADDAR, ADDIA

1 = A carry from the 4

th low order bit of the result occurred.

0 = A carry from the 4

th low order bit of the result did not occur.

SUBAR, SUBIA

1 = A borrow from the 4

th low order bit of the result did not occur.

0 = A borrow from the 4

th low order bit of the result occurred.

Bit[0] : C

Carry flag or borrow flag.

ADDAR, ADDIA, RLR

1 = A carry occurred.

0 = A Carry did not occur.

SUBAR, ADDIA, RRR

1 = A borrow did not occurred.

0 = A borrow occurred.

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