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FM8PC71AM Datasheet(PDF) 23 Page - Feeling Technology Corp.

Part # FM8PC71AM
Description  FTC 8-Bit Micro-Controller With 12-bits ADC
PDF  73 Pages
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Manufacturer  FEELING [Feeling Technology Corp.]
Direct Link  http://www.feeling-tech.com.tw/
Logo FEELING - Feeling Technology Corp.

FM8PC71AM Datasheet(HTML) 23 Page - Feeling Technology Corp.

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FM8PC71AM
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
P.23
R1.1.004, Aug 7, 2017
FM8PC71AM
遠翔科技
Feeling Technology
2.4.3 PortA, PortB Mode define
Address 08H: Port A Mode0 Control Register(PAMODE0)
Bits
7
6
5
4
3
2
1
0
Name
PAM0[7]
PAM0[6]
PAM0[5]
PAM0[4]
PAM0[3]
PAM0[2]
PAM0[1]
PAM0[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Accessed by IOST/IOSTR instruction
Bit[7:0] : PA [7:0] Mode0
1 = Port pin Mode 0 is logic HIGH
0 = Port pin Mode 0 is logic LOW
Address 09H: Port A Mode1 Control Register(PAMODE1)
Bits
7
6
5
4
3
2
1
0
Name
PAM1[7]
PAM1[6]
PAM1[5]
PAM1[4]
PAM1[3]
PAM1[2]
PAM1[1]
PAM1[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
1
0
0
Accessed by IOST/IOSTR instruction
Bit[7:0] : PA [7:0] Mode 1
1 = Port pin Mode 1 is logic HIGH
0 = Port pin Mode 1 is logic LOW
Note: PA[2] default is pull high
Address 0AH: Port B Mode1 Control Register(PBMODE0)
Bits
7
6
5
4
3
2
1
0
Name
--
--
PBM0[5]
PBM0[4]
PBM0[3]
PBM0[2]
PBM0[1]
PAM0[0]
Read/Write
--
--
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Accessed by IOST/IOSTR instruction
Bit[7:0] : PB [5:0] Mode 0
1 = Port pin Mode 0 is logic HIGH
0 = Port pin Mode 0 is logic LOW
Address 0BH: Port B Mode1 Control Register(PBMODE1)
Bits
7
6
5
4
3
2
1
0
Name
--
--
PBM1[5]
PBM1[4]
PBM1[3]
PBM1[2]
PBM1[1]
PBM1[0]
Read/Write
--
--
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Accessed by IOST/IOSTR instruction
Bit[7:0] : PB [5:0] Mode 1
1 = Port pin Mode 1 is logic HIGH
0 = Port pin Mode 1 is logic LOW
Note: When chip is power on reset (VDD < POR), the PB[0] is pull-high mode(pull high 100K).
When chip is after power on reset (VDD > POR), the PB[0] is input mode.



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