EM785830AA

8-bit Micro-controller

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* This specification is subject to be changed without notice.

10

12/1/2004

V1.6

Fsco=0.895MHz/2

If PLL is disabled, the instruction clock is 32.768kHz/2

Fsco=32.768kHz/2.

Bit 3 (SCES) : SPI clock edge selection bit

1

Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.

0

Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.

Bit 4 (SE) : SPI shift enable bit

1

Start to shift, and keep on 1 while the current byte is still being transmitted.

0

Reset as soon as the shifting is complete, and the next byte is ready to shift.

<Note> This bit has to be reset in software.

Bit 5 (SRO) : SPI read overflow bit

1

A new data is received while the previous data is still being hold in the SPIB register. In this situation,

the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB

register even if the transmission is implemented only.

0

No overflow,

<Note> This can only occur in slave mode.

Bit 6 (SPIE) : SPI enable bit

1

Enable SPI mode

0

Disable SPI mode

Bit 7 (RBF) : SPI read buffer full flag

1

Receive is finished, SPIB is full.

0

Receive is not finish yet, SPIB is empty.

Bit 0

SPI module

SCK

Bit7

Salve Device

SPIR register

SDI

SPIW register

SPIS Reg

SDO

SDO

SCK

SDI

Master Device

R5 page1

Fig.4 Single SPI Master / Salve Communication

Fig. 4 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it

sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI,

however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be

shifted on a basis of both the clock rate and the selected edge.