MCP18480 datasheet(44/64 Pages) MICROCHIP

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MCP18480

DS20091B-page 44

 2003 Microchip Technology Inc.

6.8

DESCRIPTION OF INTERNAL

BLOCKS

The internal blocks shown in the MCP18480 Block Dia-

gram on page 2 are discussed in Section 6.8.1 through

Section 6.8.8.

6.8.1

UV (UNDERVOLTAGE) BLOCK

The Undervoltage lockout circuit monitors the input

voltage by comparing a centertap voltage on an exter-

nal resistor divider to a 2.5V reference. The centertap

voltage is fed into the UVTH input pin.

If the voltage on the UVTH pin is below the internal 2.5V

reference, the absolute magnitude of the supply volt-

age is too low for proper system operation, resulting in

the external MOSFET being turned off. If the voltage on

the UVTH pin is greater than VNEG + 2.5V, the supply

voltage is above the minimal operating voltage as set

by the external resistor divider network.

In telecom network applications, it is common to shut

down the DC/DC converter supply when the input volt-

age falls below -38.5V (tolerance of ±1.0V) for greater

than 100 ms. The system will not restart until the volt-

age exceeds -43.0V (tolerance of ±0.5V). This voltage

difference is produced by an open-drain NMOS output

(the UVHYS pin) that connects an external resistor in

parallel with the lower of the two resistors in the exter-

nal UV divider network until the supply ramps down to

-43V. When the UVTH pin exceeds VNEG + 2.5V, the

internal NMOS transistor is turned off, disconnecting

the external resistor connected to the UVHYS pin. The

voltage at the UVTH pin increases to 2.79V. The supply

voltage would have to decrease to -38.5V in order to

assert the internal “Undervoltage Active” signal.

An internal 10 µA current source and an external

capacitor connected to the UVD pin adjusts the delay

between the input fault and the notification of this fault

to the system. This is usually 100 ms for -48V telecom-

type equipment. For customized adjustments, the time

delay can be expressed as Equation 6-1.

EQUATION 6-1:

INPUT FAULT DELAY

CUV is the capacitor connected between the UVD pin

and the VNEG pin. A value of 1 µF would provide a

delay of about 100 ms.

If the supply voltage dips below the programmed

threshold, the input comparator trips the other way. The

timing capacitor is released to ramp-up at the previ-

ously described rate and the Undervoltage block

switches when the capacitor voltage reaches 1.25V.

When the input comparator goes to a low level, the hys-

teresis FET is turned on and the trip point for

reassertion of good VNEG reverts to -43V.

While the Undervoltage Active signal is low (includes

Undervoltage input filter), the GATE pin driver for the

external MOSFET is disabled, the GATE pin is pulled to

the voltage of the VNEG pin with a 60 mA current sink

and the PWRGOOD output pin is deasserted to indi-

cate that the input voltage is out of range.

EQUATION 6-2:

UNDERVOLTAGE

HYSTERESIS

EQUATION 6-3:

UNDERVOLTAGE

CONDITION

Note:

Voltage levels discussed are with respect

to external component values selected in

Figure 4-1.

TDELAY

VREFIN

------------------



 C

UVD

•

µA

--------------------------------------------

RUVHYS

RUV1

VUVD

VREFIN

------------------



 RUV1

RUV2

------------- 1

–

----------------------------------------------------

RUVHYS

RUV1

VUVD

VREFIN

------------------



 RUV1

RUV2

------------- 1

–

----------------------------------------------------

VREFIN

VNEG RUV2

•

RUV1 RUV2

()

-------------------------------------

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