MCP18480 datasheet(45/64 Pages) MICROCHIP

45 / 64 page

 2003 Microchip Technology Inc.

DS20091B-page 45

MCP18480

6.8.2

OV (OVERVOLTAGE) BLOCK

The overvoltage block behaves similarly to the under-

voltage block in that it monitors an input voltage by

comparing a centertap voltage on an external voltage

divider (on the OVTH pin) to the VREFIN pin voltage.

If the centertap voltage is below the reference, the input

voltage is not excessive. If the centertap voltage is

greater than the VNEG + VREFIN pin voltages, the sup-

ply voltage is higher than the programmed acceptable

maximum voltage limit. An internal flag is then acti-

vated to inform the MCP18480 that the input voltage

has exceeded the preset limit.

The “Overvoltage Active” signal deasserts when the

input voltage drops back below the threshold

determined by the external resistors (ROV1 and ROV2).

EQUATION 6-4:

OVERVOLTAGE VOLTAGE

CONDITION

6.8.3

FET-GOOD BLOCK

The FET-good block monitors the voltage between the

drain of the external MOSFET and on the VNEG pin at

power-up. It delays assertion of PWRGOOD until the

drain-to-source voltage of the external FET is accept-

ably low and the voltage at the GATE pin is about 8V.

The comparator operation is similar to Undervoltage

and Overvoltage blocks.

To prevent applying excessive voltages to the gates of

the FETs in the Undervoltage circuit, a resistive voltage

divider is employed between ground and the VNEG pin.

Similarly, the drain of the external MOSFET can be

exposed to voltages at around VNEG during normal

operation and as high as ground (typically 48V above

VNEG).

The FET good block also monitors the GATE pin. When

the GATE pin becomes >VNEG +8V and the DRAINTH

pin is within its programmed range, the output of the

FET good block is active.

The internal FET good signal goes high and remains

active until a fault condition (Undervoltage, Overvolt-

age or Current Limit) is detected. Any of these condi-

tions hold the PWRGOOD signal deasserted until the

fault condition is removed and the external FET gate

and drain voltages are acceptable.

VREFIN

VNEG ROV2

•

ROV1 ROV2

()

-------------------------------------

MCP18480 Datasheet(PDF) 45 Page - Microchip Technology

MCP18480 Datasheet(HTML) 45 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL