845GL datasheet(109/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

109

Functional Description

Memory Detection and Initialization

Before any cycles to the memory interface can be supported, the GMCH SDRAM registers must be

initialized. The GMCH must be configured for operation with the installed memory types.

Detection of memory type and size is done via the System Management Bus (SMB) interface on

the ICH4. This two-wire bus is used to extract the SDRAM type and size information from the

Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin Serial

Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0]. Devices

on the SMBus bus have a 7-bit address. For the SDRAM DIMMs, the upper four bits are fixed at

1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected to the

System Management Bus on the ICH4. Thus, data is read from the Serial Presence Detect port on

the DIMMs via a series of I/O cycles to the ICH4. BIOS needs to determine the size and type of

memory used for each of the rows of memory to properly configure the GMCH memory interface.

SMBus Configuration and Access of the Serial Presence Detect Ports

For more details, refer to the Intel® 82801DB I/O Controller Hub 4 (ICH4) Datasheet.

Memory Register Programming

This section provides an overview of how the required information for programming the SDRAM

registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence

Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a

row by row basis), SDRAM Timings, Row Sizes, and Row Page Sizes. Table 4-4 lists a subset of

the data available through the on board Serial Presence Detect ROM on each DIMM. Table 4-4 is

only a subset of the defined SPD bytes on the DIMMs. These bytes collectively provide enough

data for programming the GMCH SDRAM registers.

4.2.4

Memory Address Translation and Decoding

The GMCH contains address decoders that translate the address received on the host bus or the hub

interface. Decoding and translation of these addresses vary with the four SDRAM types. Also, the

number of pages, page sizes, and densities supported vary with the type. The GMCH supports

64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM devices. The multiplexed row/column address to

the SDRAM memory array is provided by the memory bank select and memory address signals.

These addresses are derived from the host address bus as defined by Table 4-5 for SDRAM

devices.

Table 4-4. Data Bytes on DIMM Used for Programming DRAM Registers

Byte

Function

Memory Type (SDR SDRAM or DDR SDRAM)

Number of Row Addresses, not counting Bank Addresses

Number of Column Addresses

Number of banks of SDRAM (single- or double-sided DIMM)

ECC, non-ECC (GMCH does not support ECC)

Refresh rate

Number of Banks on each device

845GL Datasheet(PDF) 109 Page - Intel Corporation

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