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Intel® 82845G/82845GL/82845GV GMCH Datasheet

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Functional Description

This chapter describes the GMCH interfaces and functional units including the processor system

bus interface, the AGP interface, system memory controller, integrated graphics device, DVO

interfaces, display interfaces, power management, and clocking.

4.1

Processor System Bus

The GMCH supports a single mPGA 478 processor with PSB frequencies of 400 MHz (100 MHz

HCLK) / 533 MHz (133 MHz HCLK) and it also supports Hyper-Threading Technology. The

GMCH uses a scalable PSB VTT between 1.15 V and 1.75 V and on-die termination. The GMCH

supports 32-bit host addressing (decoding up to 4 GB of the processor’s memory address space).

Host-initiated I/O cycles are decoded to the AGP/PCI_B, hub interface or GMCH configuration

space. Host-initiated memory cycles are decoded to AGP/PCI_B, the hub interface, or system

memory. All memory accesses from the host interface that hit the graphics aperture are translated

using an AGP address translation table. AGP/PCI_B device accesses to non-cacheable system

memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_B using PCI

semantics and from the hub interface to system memory are snooped on the host bus.

The GMCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. The

cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals. At

100/133 MHz bus clock the address signals are double pumped to run at 200/266 MHz and a new

address can be generated every other bus clock. At 100/133 MHz bus clock the data signals are

quad pumped to run at 400/533 MHz and an entire 64-B cache line can be transferred in two bus

clocks.

The GMCH integrates AGTL+ termination resistors on die. The GMCH has an IOQ depth of 8.

The GMCH supports one outstanding Deferred transaction on the PSB.

4.1.1

PSB Dynamic Bus Inversion

The GMCH supports Dynamic Bus Inversion (DBI) when driving, and when receiving data from

the system bus. DBI limits the number of data signals that are driven to a low voltage on each quad

pumped data phase. This decreases the power consumption of the GMCH. DINV_[3:0]# indicate if

the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase

(see Table 4-1).

Table 4-1. DINV Signals vs. Data Bytes

DINV[3:0]#

Data Bits

DINV_0#

HD_[15:0]#

DINV_1#

HD_[31:16]#

DINV_2#

HD_[47:32]#

DINV_3#

HD_[63:48]#

845GL Datasheet(PDF) 105 Page - Intel Corporation

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