845GL datasheet(106/193 Pages) INTEL

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Functional Description

106

Intel® 82845G/82845GL/82845GV GMCH Datasheet

When the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of

the 16 signals would normally be driven low on the bus, the corresponding DINV# signal is

asserted and the data is inverted prior to being driven on the bus. When the processor or the GMCH

receives data, it monitors DINV[3:0]# to determine if the corresponding data segment should be

inverted.

4.1.2

System Bus Interrupt Delivery

Pentium 4 processors support system bus interrupt delivery. They do not support the APIC serial

bus interrupt delivery mechanism. Interrupt-related messages are encoded on the system bus as

“Interrupt Message Transactions.” In an 845G chipset, system bus interrupts can originate from the

processor on the system bus, or from a downstream device on hub interface, or AGP. In the later

case the GMCH drives the “Interrupt Message Transaction” on the system bus.

In an 845G chipset, the ICH4 contains IOxAPICs, and its interrupts are generated as upstream hub

interface memory writes. Furthermore, PCI Local Bus Specification, Revision 2.2 defines MSIs

(Message Signaled Interrupts) that are also in the form of memory writes. A PCI Local Bus

Specification, Revision 2.2 device can generate an interrupt as an MSI cycle on it’s PCI bus instead

of asserting a hardware signal to the IOxAPIC. The MSI can be directed to the IOxAPIC, which in

turn generates an interrupt as an upstream hub interface memory write. Alternatively, the MSI can

be directed directly to the system bus. The target of an MSI is dependent on the address of the

interrupt memory write. The GMCH forwards inbound hub interface and AGP (PCI semantic only)

memory writes to address 0FEEx_xxxxh, to the system bus as “Interrupt Message Transactions.”

4.1.3

Upstream Interrupt Messages

The GMCH accepts message based interrupts from AGP (PCI semantics only) or its hub interface,

and forwards them to the system bus as Interrupt Message Transactions. The interrupt messages

presented to the GMCH are in the form of memory writes to address 0FEEx_xxxxh. At the hub

interface or AGP interface, the memory write interrupt message is treated like any other memory

write; it is either posted into the inbound data buffer (if space is available) or retried (if data buffer

space is not immediately available). Once posted, the memory write from AGP or the hub

interface, to address 0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by the

GMCH to the system bus as an Interrupt Message Transaction.

845GL Datasheet(PDF) 106 Page - Intel Corporation