845GL datasheet(107/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

107

Functional Description

4.2

System Memory Controller

The GMCH can be configured to support either SDR SDRAM or DDR SDRAM memory.

4.2.1

DDR SDRAM Interface Overview

The GMCH can support DDR266 and DDR200 in DDR mode with SSTL_2 signaling. The GMCH

includes support for:

• Up to 2 GB of 266 MHz or 200 MHz DDR SDRAM

• DDR266 or DDR200 unbuffered 184-pin non-ECC DDR SDRAM DIMMs

• Maximum of two DIMMs, single-sided and/or double-sided

• Byte masking on writes through data masking

The bank address lines and the address lines allow the GMCH to support 64-bit wide DIMMs using

64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM technology. The four chip select lines support up

to four rows of double-sided SDRAM DIMMs. For write operations of less than a QWord, the

GMCH performs a byte-wise write. The GMCH does not support ECC DIMMs, registered

DIMMs, or double-sided x16 DIMMs.

4.2.2

SDR SDRAM Interface Overview

In addition to DDR SDRAM, the GMCH can support PC133 with LVTTL signaling. The GMCH

integrates a main memory SDRAM controller with a 64-bit wide interface and 8 system memory

clock signals, each at 133 MHz for SDR SDRAM. The GMCH supports the following:

• Up to 2 GB of 133 MHz SDR SDRAM.

• PC133 unbuffered 168-pin non-ECC SDR SDRAM DIMMs.

• Maximum of two DIMMs, single-sided and/or double-sided.

• Byte masking on writes through data masking

The bank address lines and the address lines allow the GMCH to support 64-bit wide DIMMs using

64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM technology. The eight chip select lines support up

to four rows of double-sided SDRAM DIMMs. For write operations of less than a QWord, the

GMCH performs a byte-wise write. The GMCH does not support ECC DIMMs, registered

DIMMs, mixed-mode (uneven) DS DIMMs, or PC100 DIMMs.

845GL Datasheet(PDF) 107 Page - Intel Corporation