82845MP datasheet(83/157 Pages) INTEL

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Intel

® 82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

3.7.37.

SMICMD – SMI Command Register – Device #0

Address Offset:

CC-CDh

Default Value:

0000h

Access:

Read/Write, Read Only

Size:

16 bits

This register enables various errors to generate an SMI message via the hub interface A.

Note: An error can generate one and only one error message via the hub interface A. It is software’s

responsibility to make sure that when an SMI error message is enabled for an error condition; SERR and

SCI error messages are disabled for that same error condition.

Bit

Description

15:2

Reserved

SMI on Multiple-bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub

interface A SMI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.

For systems not supporting ECC this bit must be disabled.

SMI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A

SMI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems

that do not support ECC this bit must be disabled.

3.7.38.

SCICMD – SCI Command Register – Device #0

Address Offset:

CE-CDh

Default Value:

0000h

Access:

Read/Write, Read Only

Size:

16 bits

This register enables various errors to generate a SCI message via the hub interface A.

Note: An error can generate one and only one error message via the hub interface A. It is software’s

responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and

SMI error messages are disabled for that same error condition.

Bit

Description

15:2

Reserved

SCI on Multiple-Bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub

interface A SCI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.

For systems not supporting ECC this bit must be disabled.

SCI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A

SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems

that do not support ECC this bit must be disabled.

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