82845MP datasheet(18/157 Pages) INTEL

18 / 157 page

Intel

®82845MP/82845MZ Chipset-Mobile (MCH-M)

Datasheet

250687-002

1.4.

AGP Interface

A single AGP component or connector (not both) is supported by the Intel 845MP/845MZ Chipset

MCH-M AGP interface. The AGP buffers operate only in 1.5-V mode. They are not 3.3-V safe.

The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x Fast Writes. AGP semantic cycles to

DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on the host bus. The

MCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the

PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and

downstream addressing is limited to 32 bits for AGP and AGP/PCI transactions. The MCH-M contains a

32-deep AGP request queue. High priority accesses are supported. All accesses from the AGP/PCI

interface that fall within the Graphics Aperture address range pass through an address translation

mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited

to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked

from a dedicated 66MHz clock (66IN). The AGP-to-host/core interface is asynchronous.

Consult the latest AGP Busy and Stop Protocol Specification for more information.

1.5.

Hub Interface

The 8-bit hub interface connects the MCH-M to the ICH3-M. All communication between the MCH-M

and the ICH3-M occurs over the hub interface. The hub interface runs at 66 MHz/266 MB/s. Aside from

the obvious traffic types, the following communication also occur over hub interface:

• Interrupt related messages

• Power management events as messages

• SMI, SCI, and SERR error indication messages

It is assumed that the hub interface is always connected to an ICH3-M. This is a proprietary interconnect

between the MCH-M and the ICH3-M.

1.6.

MCH-M Clocking

The MCH-M has the following clock input pins:

• Differential BCLK[1:0] for the host interface

• 66-MHz clock input for the AGP and hub interface

Clock Synthesizer chip(s) are responsible for generating the system Host clocks, AGP and hub interface

clocks, PCI clocks, and DRAM clocks. The Host target speed is 400 MT/s. The MCH-M does not

require any relationship between the HCLKIN host clock and the 66-MHz clock generated for AGP and

hub interface; they are totally asynchronous from each other. The AGP and hub interface runs at a

constant 66-MHz base frequency. The hub interface runs at 4x, while AGP transfers may be 1x, 2x, or

4x.

The following tables indicate the frequency ratios between the various interfaces that the MCH-M

supports.

82845MP Datasheet(PDF) 18 Page - Intel Corporation

82845MP Datasheet(HTML) 18 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL